Add in Context IDs to the simulator. From now on, cpuId is almost never used,

the primary identifier for a hardware context should be contextId().  The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.

4 files changed, 8 insertions, 8 deletions

diff --git a/src/arch/alpha/locked_mem.hh b/src/arch/alpha/locked_mem.hh
index 6f4f5a748..e8928ba08 100644
--- a/src/arch/alpha/locked_mem.hh
+++ b/src/arch/alpha/locked_mem.hh
@@ -85,9 +85,9 @@ handleLockedWrite(XC *xc, Request *req)
             stCondFailures++;
             xc->setStCondFailures(stCondFailures);
             if (stCondFailures % 100000 == 0) {
-                warn("cpu %d: %d consecutive "
+                warn("context %d: %d consecutive "
                      "store conditional failures\n",
-                     xc->cpuId(), stCondFailures);
+                     xc->contextId(), stCondFailures);
             }
 
             // store conditional failed already, so don't issue it to mem
diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh
index 5877b1439..9f41ba075 100644
--- a/src/arch/mips/locked_mem.hh
+++ b/src/arch/mips/locked_mem.hh
@@ -83,9 +83,9 @@ handleLockedWrite(XC *xc, Request *req)
             stCondFailures++;
             xc->setStCondFailures(stCondFailures);
             if (stCondFailures % 10 == 0) {
-                warn("%i: cpu %d: %d consecutive "
+                warn("%i: context %d: %d consecutive "
                      "store conditional failures\n",
-                     curTick, xc->cpuId(), stCondFailures);
+                     curTick, xc->contextId(), stCondFailures);
             }
 
             if (stCondFailures == 5000) {
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index 6961a24e9..502033d97 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -257,11 +257,11 @@ MiscRegFile::readFSReg(int miscReg, ThreadContext * tc)
         temp = readRegNoEffect(miscReg) & (STS::active | STS::speculative);
         // Check that the CPU array is fully populated
         // (by calling getNumCPus())
-        assert(sys->getNumCPUs() > tc->cpuId());
+        assert(sys->getNumContexts() > tc->contextId());
 
-        temp |= tc->cpuId()  << STS::shft_id;
+        temp |= tc->contextId()  << STS::shft_id;
 
-        for (x = tc->cpuId() & ~3; x < sys->threadContexts.size(); x++) {
+        for (x = tc->contextId() & ~3; x < sys->threadContexts.size(); x++) {
             switch (sys->threadContexts[x]->status()) {
               case ThreadContext::Active:
                 temp |= STS::st_run << (STS::shft_fsm0 -
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 17374fa0c..4980c5fe5 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -654,7 +654,7 @@ TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
         */
         // Force the access to be uncacheable.
         req->setFlags(req->getFlags() | UNCACHEABLE);
-        req->setPaddr(x86LocalAPICAddress(tc->cpuId(), paddr - baseAddr));
+        req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr));
     }
 #endif
     return NoFault;