gpu-compute: support in-order data delivery in GM pipe

this patch adds an ordered response buffer to the GM pipeline
to ensure in-order data delivery. the buffer is implemented as
a stl ordered map, which sorts the request in program order by
using their sequence ID. when requests return to the GM pipeline
they are marked as done. only the oldest request may be serviced
from the ordered buffer, and only if is marked as done.

the FIFO response buffers are kept and used in OoO delivery mode

3 files changed, 12 insertions, 12 deletions

diff --git a/src/arch/hsail/insts/decl.hh b/src/arch/hsail/insts/decl.hh
index c40411ace..4c0bc9ce1 100644
--- a/src/arch/hsail/insts/decl.hh
+++ b/src/arch/hsail/insts/decl.hh
@@ -1082,7 +1082,7 @@ namespace HsailISA
 
                 gpuDynInst->useContinuation = false;
                 GlobalMemPipeline* gmp = &(w->computeUnit->globalMemoryPipe);
-                gmp->getGMReqFIFO().push(gpuDynInst);
+                gmp->issueRequest(gpuDynInst);
 
                 w->wrGmReqsInPipe--;
                 w->rdGmReqsInPipe--;
diff --git a/src/arch/hsail/insts/mem_impl.hh b/src/arch/hsail/insts/mem_impl.hh
index c175f2782..dbda6643b 100644
--- a/src/arch/hsail/insts/mem_impl.hh
+++ b/src/arch/hsail/insts/mem_impl.hh
@@ -263,7 +263,7 @@ namespace HsailISA
                 }
             }
 
-            w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
+            w->computeUnit->globalMemoryPipe.issueRequest(m);
             w->outstandingReqsRdGm++;
             w->rdGmReqsInPipe--;
             break;
@@ -288,7 +288,7 @@ namespace HsailISA
                 }
             }
 
-            w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
+            w->computeUnit->globalMemoryPipe.issueRequest(m);
             w->outstandingReqsRdGm++;
             w->rdGmReqsInPipe--;
             break;
@@ -312,7 +312,7 @@ namespace HsailISA
                 }
             }
 
-            w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
+            w->computeUnit->globalMemoryPipe.issueRequest(m);
             w->outstandingReqsRdGm++;
             w->rdGmReqsInPipe--;
             break;
@@ -330,7 +330,7 @@ namespace HsailISA
                     }
                 }
             }
-            w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
+            w->computeUnit->globalMemoryPipe.issueRequest(m);
             w->outstandingReqsRdGm++;
             w->rdGmReqsInPipe--;
             break;
@@ -440,7 +440,7 @@ namespace HsailISA
                 }
             }
 
-            w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
+            w->computeUnit->globalMemoryPipe.issueRequest(m);
             w->outstandingReqsWrGm++;
             w->wrGmReqsInPipe--;
             break;
@@ -460,7 +460,7 @@ namespace HsailISA
                 }
             }
 
-            w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
+            w->computeUnit->globalMemoryPipe.issueRequest(m);
             w->outstandingReqsWrGm++;
             w->wrGmReqsInPipe--;
             break;
@@ -486,7 +486,7 @@ namespace HsailISA
                 }
             }
 
-            w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
+            w->computeUnit->globalMemoryPipe.issueRequest(m);
             w->outstandingReqsWrGm++;
             w->wrGmReqsInPipe--;
             break;
@@ -591,7 +591,7 @@ namespace HsailISA
             m->latency.set(w->computeUnit->shader->ticks(64));
             m->pipeId = GLBMEM_PIPE;
 
-            w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
+            w->computeUnit->globalMemoryPipe.issueRequest(m);
             w->outstandingReqsWrGm++;
             w->wrGmReqsInPipe--;
             w->outstandingReqsRdGm++;
diff --git a/src/arch/hsail/insts/pseudo_inst.cc b/src/arch/hsail/insts/pseudo_inst.cc
index bfffb7d8f..580328aed 100644
--- a/src/arch/hsail/insts/pseudo_inst.cc
+++ b/src/arch/hsail/insts/pseudo_inst.cc
@@ -648,7 +648,7 @@ namespace HsailISA
 
         m->pipeId = GLBMEM_PIPE;
         m->latency.set(w->computeUnit->shader->ticks(64));
-        w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
+        w->computeUnit->globalMemoryPipe.issueRequest(m);
         w->outstandingReqsWrGm++;
         w->wrGmReqsInPipe--;
         w->outstandingReqsRdGm++;
@@ -688,7 +688,7 @@ namespace HsailISA
 
         m->pipeId = GLBMEM_PIPE;
         m->latency.set(w->computeUnit->shader->ticks(64));
-        w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
+        w->computeUnit->globalMemoryPipe.issueRequest(m);
         w->outstandingReqsWrGm++;
         w->wrGmReqsInPipe--;
         w->outstandingReqsRdGm++;
@@ -727,7 +727,7 @@ namespace HsailISA
 
         m->pipeId = GLBMEM_PIPE;
         m->latency.set(w->computeUnit->shader->ticks(1));
-        w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
+        w->computeUnit->globalMemoryPipe.issueRequest(m);
         w->outstandingReqsRdGm++;
         w->rdGmReqsInPipe--;
         w->outstandingReqs++;