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authorGabe Black <gblack@eecs.umich.edu>2008-10-09 00:04:36 -0700
committerGabe Black <gblack@eecs.umich.edu>2008-10-09 00:04:36 -0700
commit569db520ad69bc8b3f506accb0a86d1e519e63ad (patch)
treee06fa0a1b4de3b1b6389c20d922b7128ae97206e /src/arch
parentb423c7a103ea1952353436e9309e49b6c3fff85a (diff)
downloadgem5-569db520ad69bc8b3f506accb0a86d1e519e63ad.tar.xz
X86: Make far ret modify CS instead of some random selector.
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py b/src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py
index b18d48264..d1a8245e6 100644
--- a/src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py
+++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py
@@ -109,8 +109,8 @@ processDescriptor:
chks t2, t3, IretCheck, dataSize=8
# There should be validity checks on the RIP checks here, but I'll do
# that later.
- wrdl reg, t3, t2
- wrsel reg, t2
+ wrdl cs, t3, t2
+ wrsel cs, t2
wrip t0, t1
bri t0, label("end")