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author | Gabe Black <gblack@eecs.umich.edu> | 2009-08-17 20:22:56 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-08-17 20:22:56 -0700 |
commit | 90786e43fc8ba16d6e1941ca996e82e94f186e5e (patch) | |
tree | 6d524f7c1d0e2ffa55bb253ebb0b6883578d437f /src/arch | |
parent | 4c23e631f26f4195212df94684b347fe3639d3fe (diff) | |
download | gem5-90786e43fc8ba16d6e1941ca996e82e94f186e5e.tar.xz |
X86: Implement a microop that moves sign bits.
Diffstat (limited to 'src/arch')
-rw-r--r-- | src/arch/x86/isa/microops/mediaop.isa | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/arch/x86/isa/microops/mediaop.isa b/src/arch/x86/isa/microops/mediaop.isa index 981ffc74b..bef661848 100644 --- a/src/arch/x86/isa/microops/mediaop.isa +++ b/src/arch/x86/isa/microops/mediaop.isa @@ -330,6 +330,23 @@ let {{ } ''' + class Movsign(MediaOp): + def __init__(self, dest, src, \ + size = None, destSize = None, srcSize = None, ext = None): + super(Movsign, self).__init__(dest, src,\ + "InstRegIndex(0)", size, destSize, srcSize, ext) + code = ''' + int items = sizeof(FloatRegBits) / srcSize; + uint64_t result = 0; + int offset = (ext & 0x1) ? items : 0; + for (int i = 0; i < items; i++) { + uint64_t picked = + bits(FpSrcReg1.uqw, (i + 1) * 8 * srcSize - 1); + result = insertBits(result, i + offset, i + offset, picked); + } + DestReg = DestReg | result; + ''' + class Unpack(MediaOp): code = ''' assert(srcSize == destSize); |