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authorGabe Black <gblack@eecs.umich.edu>2009-02-25 10:18:58 -0800
committerGabe Black <gblack@eecs.umich.edu>2009-02-25 10:18:58 -0800
commitc849ef58c05e00e8523d6f2a9d8f0da6315e75d9 (patch)
treec918bd35bfb04d7a12ce6ab3d25205ae46f494aa /src/arch
parentf35a37ca9eb7ff25c0da5ec14b83f77f5321222c (diff)
downloadgem5-c849ef58c05e00e8523d6f2a9d8f0da6315e75d9.tar.xz
X86: Actually check page protections.
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/x86/tlb.cc12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 372c8b997..603d4e45f 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -649,6 +649,18 @@ TLB::translate(RequestPtr req, ThreadContext *tc,
#endif
}
// Do paging protection checks.
+ bool inUser = (csAttr.dpl == 3 &&
+ !(flags & (CPL0FlagBit << FlagShift)));
+ if (inUser && !entry->user ||
+ write && !entry->writable) {
+ // The page must have been present to get into the TLB in
+ // the first place. We'll assume the reserved bits are
+ // fine even though we're not checking them.
+ return new PageFault(vaddr, true, write,
+ inUser, false, execute);
+ }
+
+
DPRINTF(TLB, "Entry found with paddr %#x, "
"doing protection checks.\n", entry->paddr);
Addr paddr = entry->paddr | (vaddr & (entry->size-1));