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authorNathan Binkert <nate@binkert.org>2008-06-14 12:57:21 -0700
committerNathan Binkert <nate@binkert.org>2008-06-14 12:57:21 -0700
commitce43e46576ccf09d56aeb7021d3decd75d08d90c (patch)
tree468de5493ff8a12ffbca48ee01e7b80953bd69b1 /src/arch
parent7a58b5a38a15b5e025435820a2679c34eb2c47a4 (diff)
downloadgem5-ce43e46576ccf09d56aeb7021d3decd75d08d90c.tar.xz
Fix various SWIG warnings
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/mips/MipsTLB.py4
-rw-r--r--src/arch/x86/X86TLB.py2
2 files changed, 1 insertions, 5 deletions
diff --git a/src/arch/mips/MipsTLB.py b/src/arch/mips/MipsTLB.py
index ce8847365..1d0244e22 100644
--- a/src/arch/mips/MipsTLB.py
+++ b/src/arch/mips/MipsTLB.py
@@ -33,10 +33,8 @@ from m5.SimObject import SimObject
from m5.params import *
class MipsTLB(SimObject):
- abstract = True
type = 'MipsTLB'
- cxx_namespace = 'MipsISA'
- cxx_class = 'TLB'
+ abstract = True
size = Param.Int("TLB size")
class MipsDTB(MipsTLB):
diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py
index dc080f37e..8dd53620e 100644
--- a/src/arch/x86/X86TLB.py
+++ b/src/arch/x86/X86TLB.py
@@ -69,8 +69,6 @@ if build_env['FULL_SYSTEM']:
class X86TLB(SimObject):
type = 'X86TLB'
- cxx_namespace = 'X86ISA'
- cxx_class = 'TLB'
abstract = True
size = Param.Int("TLB size")
if build_env['FULL_SYSTEM']: