Rename cycles() function to ticks()

--HG--
extra : convert_revision : 790eddb793d4f5ba35813d001037bd8601bd76a5

4 files changed, 12 insertions, 12 deletions

diff --git a/src/arch/mips/regfile/misc_regfile.cc b/src/arch/mips/regfile/misc_regfile.cc
index 02e9c92bb..82f284ec4 100755
--- a/src/arch/mips/regfile/misc_regfile.cc
+++ b/src/arch/mips/regfile/misc_regfile.cc
@@ -304,7 +304,7 @@ MiscRegFile::scheduleCP0Update(int delay)
 
         //schedule UPDATE
         CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0);
-        cp0_event->schedule(curTick + cpu->cycles(delay));
+        cp0_event->schedule(curTick + cpu->ticks(delay));
     }
 }
 
@@ -364,9 +364,9 @@ void
 MiscRegFile::CP0Event::scheduleEvent(int delay)
 {
     if (squashed())
-        reschedule(curTick + cpu->cycles(delay));
+        reschedule(curTick + cpu->ticks(delay));
     else if (!scheduled())
-        schedule(curTick + cpu->cycles(delay));
+        schedule(curTick + cpu->ticks(delay));
 }
 
 void
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 093e0356b..b6880ff94 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -1033,7 +1033,7 @@ doMmuReadError:
             (uint32_t)asi, va);
     }
     pkt->makeAtomicResponse();
-    return tc->getCpuPtr()->cycles(1);
+    return tc->getCpuPtr()->ticks(1);
 }
 
 Tick
@@ -1280,7 +1280,7 @@ doMmuWriteError:
             (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
     }
     pkt->makeAtomicResponse();
-    return tc->getCpuPtr()->cycles(1);
+    return tc->getCpuPtr()->ticks(1);
 }
 
 #endif
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index 48e97a531..fe733813c 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -85,7 +85,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
         if (!(tick_cmpr & ~mask(63)) && time > 0) {
             if (tickCompare->scheduled())
                 tickCompare->deschedule();
-            tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
+            tickCompare->schedule(time * tc->getCpuPtr()->ticks(1));
         }
         panic("writing to TICK compare register %#X\n", val);
         break;
@@ -101,7 +101,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
         if (!(stick_cmpr & ~mask(63)) && time > 0) {
             if (sTickCompare->scheduled())
                 sTickCompare->deschedule();
-            sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1) + curTick);
+            sTickCompare->schedule(time * tc->getCpuPtr()->ticks(1) + curTick);
         }
         DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
         break;
@@ -171,7 +171,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
         if (!(hstick_cmpr & ~mask(63)) && time > 0) {
             if (hSTickCompare->scheduled())
                 hSTickCompare->deschedule();
-            hSTickCompare->schedule(curTick + time * tc->getCpuPtr()->cycles(1));
+            hSTickCompare->schedule(curTick + time * tc->getCpuPtr()->ticks(1));
         }
         DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
         break;
@@ -315,7 +315,7 @@ MiscRegFile::processSTickCompare(ThreadContext *tc)
             setReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
         }
     } else
-        sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
+        sTickCompare->schedule(ticks * tc->getCpuPtr()->ticks(1) + curTick);
 }
 
 void
@@ -341,6 +341,6 @@ MiscRegFile::processHSTickCompare(ThreadContext *tc)
         }
         // Need to do something to cause interrupt to happen here !!! @todo
     } else
-        hSTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
+        hSTickCompare->schedule(ticks * tc->getCpuPtr()->ticks(1) + curTick);
 }
 
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index ad23cb7e4..d7f9e6665 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -95,13 +95,13 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
 Tick
 DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
 {
-    return tc->getCpuPtr()->cycles(1);
+    return tc->getCpuPtr()->ticks(1);
 }
 
 Tick
 DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
 {
-    return tc->getCpuPtr()->cycles(1);
+    return tc->getCpuPtr()->ticks(1);
 }
 
 #endif