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| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2015-05-26 03:21:45 -0400 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2015-05-26 03:21:45 -0400 |
| commit | e590f0d1efe37448d16a86dd03fba1db6c0b4f65 (patch) | |
| tree | 37ecb7c68e57371d03ede73254a18b86bab595f0 /src/arch | |
| parent | a22c29b2633475cde9934d04597167f9c4b15cc2 (diff) | |
| download | gem5-e590f0d1efe37448d16a86dd03fba1db6c0b4f65.tar.xz | |
arm: implement the CONTEXTIDR_EL2 system reg.
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm/miscregs.cc | 4 | ||||
| -rw-r--r-- | src/arch/arm/miscregs.hh | 20 |
2 files changed, 15 insertions, 9 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index 729cb4e8b..3a40a27b0 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -1334,6 +1334,8 @@ bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS] = { bitset<NUM_MISCREG_INFOS>(string("11111111110000000100")), // MISCREG_CBAR_EL1 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), + // MISCREG_CONTEXTIDR_EL2 + bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), // Dummy registers // MISCREG_NOP @@ -3343,6 +3345,8 @@ decodeAArch64SysReg(unsigned op0, unsigned op1, switch (crm) { case 0: switch (op2) { + case 1: + return MISCREG_CONTEXTIDR_EL2; case 2: return MISCREG_TPIDR_EL2; } diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index 930902543..025507673 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2014 ARM Limited + * Copyright (c) 2010-2015 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -663,16 +663,17 @@ namespace ArmISA MISCREG_CPUMERRSR_EL1, // 596 MISCREG_L2MERRSR_EL1, // 597 MISCREG_CBAR_EL1, // 598 + MISCREG_CONTEXTIDR_EL2, // 599 // Dummy registers - MISCREG_NOP, // 599 - MISCREG_RAZ, // 600 - MISCREG_CP14_UNIMPL, // 601 - MISCREG_CP15_UNIMPL, // 602 - MISCREG_A64_UNIMPL, // 603 - MISCREG_UNKNOWN, // 604 - - NUM_MISCREGS // 605 + MISCREG_NOP, // 600 + MISCREG_RAZ, // 601 + MISCREG_CP14_UNIMPL, // 602 + MISCREG_CP15_UNIMPL, // 603 + MISCREG_A64_UNIMPL, // 604 + MISCREG_UNKNOWN, // 605 + + NUM_MISCREGS // 606 }; enum MiscRegInfo { @@ -1344,6 +1345,7 @@ namespace ArmISA "cpumerrsr_el1", "l2merrsr_el1", "cbar_el1", + "contextidr_el2", // Dummy registers "nop", |