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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:06 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:06 -0500 |
| commit | 3cff58602ab3c088dd97c65988d336e6d50b4462 (patch) | |
| tree | 3f040258f7abd7c3df977bff7de99c7eef5702f3 /src/arch | |
| parent | 90c2284714740a5febcc338eb2d2ebc064cfeb97 (diff) | |
| download | gem5-3cff58602ab3c088dd97c65988d336e6d50b4462.tar.xz | |
ARM: Fix multiply overflow flag setting.
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm/isa/insts/mult.isa | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/arch/arm/isa/insts/mult.isa b/src/arch/arm/isa/insts/mult.isa index 1c9fe418e..4b42e6c89 100644 --- a/src/arch/arm/isa/insts/mult.isa +++ b/src/arch/arm/isa/insts/mult.isa @@ -165,6 +165,8 @@ let {{ sext<16>(bits(Reg1, 15, 0)) * sext<16>(bits(Reg2, 15, 0)) + Reg3.sw; + resTemp = bits(resTemp, 32) != + bits(resTemp, 31); ''', "overflow") buildMult4InstCc ("smladx", '''Reg0 = resTemp = sext<16>(bits(Reg1, 31, 16)) * @@ -172,6 +174,8 @@ let {{ sext<16>(bits(Reg1, 15, 0)) * sext<16>(bits(Reg2, 31, 16)) + Reg3.sw; + resTemp = bits(resTemp, 32) != + bits(resTemp, 31); ''', "overflow") buildMult4Inst ("smlal", '''resTemp = sext<32>(Reg2) * sext<32>(Reg3) + (int64_t)((Reg1.ud << 32) | Reg0.ud); @@ -246,6 +250,8 @@ let {{ sext<16>(bits(Reg1, 31, 16)) * sext<16>(bits(Reg2, 31, 16)) + Reg3.sw; + resTemp = bits(resTemp, 32) != + bits(resTemp, 31); ''', "overflow") buildMult4InstCc ("smlsdx", '''Reg0 = resTemp = sext<16>(bits(Reg1, 15, 0)) * @@ -253,6 +259,8 @@ let {{ sext<16>(bits(Reg1, 31, 16)) * sext<16>(bits(Reg2, 15, 0)) + Reg3.sw; + resTemp = bits(resTemp, 32) != + bits(resTemp, 31); ''', "overflow") buildMult4InstUnCc("smlsld", '''resTemp = sext<16>(bits(Reg2, 15, 0)) * @@ -306,12 +314,16 @@ let {{ sext<16>(bits(Reg2, 15, 0)) + sext<16>(bits(Reg1, 31, 16)) * sext<16>(bits(Reg2, 31, 16)); + resTemp = bits(resTemp, 32) != + bits(resTemp, 31); ''', "overflow") buildMult3InstCc ("smuadx", '''Reg0 = resTemp = sext<16>(bits(Reg1, 15, 0)) * sext<16>(bits(Reg2, 31, 16)) + sext<16>(bits(Reg1, 31, 16)) * sext<16>(bits(Reg2, 15, 0)); + resTemp = bits(resTemp, 32) != + bits(resTemp, 31); ''', "overflow") buildMult3InstUnCc("smulbb", '''Reg0 = resTemp = sext<16>(bits(Reg1, 15, 0)) * |