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authorGabe Black <gblack@eecs.umich.edu>2009-07-08 23:02:19 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-07-08 23:02:19 -0700
commit95392d3fb8ba579a28d5c1b0abd00b2f6e52e1d0 (patch)
tree18c2c0e8f6fff16e8f064cd1edf146034f91ef54 /src/arch
parent1d4f338b391ffea73d05758ecca771bd16625031 (diff)
downloadgem5-95392d3fb8ba579a28d5c1b0abd00b2f6e52e1d0.tar.xz
ARM: Move the remaining microops out of the decoder and into the ISA desc.
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/isa/decoder.isa16
-rw-r--r--src/arch/arm/isa/formats/macromem.isa27
-rw-r--r--src/arch/arm/isa/formats/util.isa6
3 files changed, 31 insertions, 18 deletions
diff --git a/src/arch/arm/isa/decoder.isa b/src/arch/arm/isa/decoder.isa
index f52cbe1a1..76d584858 100644
--- a/src/arch/arm/isa/decoder.isa
+++ b/src/arch/arm/isa/decoder.isa
@@ -37,19 +37,8 @@
// in the ARM ISA specification document starting with Table B.1 or 3-1
//
//
-decode COND_CODE default Unknown::unknown() {
- 0xf: decode COND_CODE {
- 0x1: decode OPCODE {
- // Just a simple trick to allow us to specify our new uops here
- 0x0: PredIntOp::mvtd_uop({{ Fd.ud = ((uint64_t) Rhi << 32)|Rlo; }},
- 'IsMicroop');
- 0x1: PredIntOp::mvfd_uop({{ Rhi = (Fd.ud >> 32) & 0xffffffff;
- Rlo = Fd.ud & 0xffffffff; }},
- 'IsMicroop');
- }
- default: Unknown::unknown(); // TODO: Ignore other NV space for now
- }
-default: decode ENCODING {
+
+decode ENCODING default Unknown::unknown() {
format DataOp {
0x0: decode SEVEN_AND_FOUR {
1: decode MISC_OPCODE {
@@ -440,5 +429,4 @@ format DataOp {
}
}
}
-}
diff --git a/src/arch/arm/isa/formats/macromem.isa b/src/arch/arm/isa/formats/macromem.isa
index be9504051..355a67ea9 100644
--- a/src/arch/arm/isa/formats/macromem.isa
+++ b/src/arch/arm/isa/formats/macromem.isa
@@ -130,6 +130,33 @@ let {{
////////////////////////////////////////////////////////////////////
//
+// Moving to/from double floating point registers
+//
+
+let {{
+ microMvtdUopIop = InstObjParams('mvtd_uop', 'MicroMvtdUop',
+ 'PredOp',
+ {'code': 'Fd.ud = (Rhi.ud << 32) | Rlo;',
+ 'predicate_test': predicateTest},
+ ['IsMicroop'])
+
+ microMvfdUopIop = InstObjParams('mvfd_uop', 'MicroMvfdUop',
+ 'PredOp',
+ {'code': '''Rhi = bits(Fd.ud, 63, 32);
+ Rlo = bits(Fd.ud, 31, 0);''',
+ 'predicate_test': predicateTest},
+ ['IsMicroop'])
+
+ header_output = BasicDeclare.subst(microMvtdUopIop) + \
+ BasicDeclare.subst(microMvfdUopIop)
+ decoder_output = BasicConstructor.subst(microMvtdUopIop) + \
+ BasicConstructor.subst(microMvfdUopIop)
+ exec_output = PredOpExecute.subst(microMvtdUopIop) + \
+ PredOpExecute.subst(microMvfdUopIop)
+}};
+
+////////////////////////////////////////////////////////////////////
+//
// Macro Memory-format instructions
//
diff --git a/src/arch/arm/isa/formats/util.isa b/src/arch/arm/isa/formats/util.isa
index ea4ffa660..b5efec568 100644
--- a/src/arch/arm/isa/formats/util.isa
+++ b/src/arch/arm/isa/formats/util.isa
@@ -106,18 +106,16 @@ output decoder {{
emit_ldfstf_uops(StaticInstPtr* microOps, int index, ExtMachInst machInst,
bool loadop, bool up, int32_t disp)
{
- MachInst newMachInst = machInst & 0xf000f000;
-
if (loadop)
{
microOps[index++] = new MicroLdrUop(machInst, 19, RN, disp);
microOps[index++] =
new MicroLdrUop(machInst, 18, RN, disp + (up ? 4 : -4));
- microOps[index++] = new Mvtd_uop(newMachInst);
+ microOps[index++] = new MicroMvtdUop(machInst);
}
else
{
- microOps[index++] = new Mvfd_uop(newMachInst);
+ microOps[index++] = new MicroMvfdUop(machInst);
microOps[index++] = new MicroStrUop(machInst, 19, RN, disp);
microOps[index++] =
new MicroStrUop(machInst, 18, RN, disp + (up ? 4 : -4));