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authorGabe Black <gblack@eecs.umich.edu>2006-10-24 15:50:41 -0400
committerGabe Black <gblack@eecs.umich.edu>2006-10-24 15:50:41 -0400
commit1b1495930c74bab639f0985c2d55f767336aa59b (patch)
tree92a13290a8d45521a20d29dd767887eb6f80fd89 /src/arch
parentef8b7713ca1b6120ae4e851877f2a9ce71296219 (diff)
downloadgem5-1b1495930c74bab639f0985c2d55f767336aa59b.tar.xz
Replace the Alpha No op with a SPARC one.
--HG-- extra : convert_revision : bed03e63dc80bf24f21bad08e6553d7aab92c7b3
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/sparc/isa_traits.hh7
1 files changed, 3 insertions, 4 deletions
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 6d5aa4251..de54e168b 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -57,12 +57,11 @@ namespace SparcISA
//This makes sure the big endian versions of certain functions are used.
using namespace BigEndianGuest;
- // Alpha Does NOT have a delay slot
+ // SPARC have a delay slot
#define ISA_HAS_DELAY_SLOT 1
- //TODO this needs to be a SPARC Noop
- // Alpha UNOP (ldq_u r31,0(r0))
- const MachInst NoopMachInst = 0x2ffe0000;
+ // SPARC NOP (sethi %(hi(0), g0)
+ const MachInst NoopMachInst = 0x01000000;
const int NumIntRegs = 32;
const int NumFloatRegs = 64;