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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:10 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:10 -0500
commit247acd93c49be2d9a677775e8684f6971b6c5364 (patch)
treeb67b5cbce884111417173e475345b2d9f942f10d /src/arch
parent3ad31f61c27b505b299295008b8f52b44ddbd499 (diff)
downloadgem5-247acd93c49be2d9a677775e8684f6971b6c5364.tar.xz
ARM: Decode the arm version of ldrexd.
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/isa/formats/mem.isa3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/arm/isa/formats/mem.isa b/src/arch/arm/isa/formats/mem.isa
index 8f2dacade..303fc02db 100644
--- a/src/arch/arm/isa/formats/mem.isa
+++ b/src/arch/arm/isa/formats/mem.isa
@@ -235,7 +235,7 @@ def format ArmSyncMem() {{
case 0x1a:
return new %(strexd)s(machInst, rt, rt2, rt2 + 1, rn, true, 0);
case 0x1b:
- return new WarnUnimplemented("ldrexd", machInst);
+ return new %(ldrexd)s(machInst, rt, rt + 1, rn, true, 0);
case 0x1c:
return new %(strexb)s(machInst, rt, rt2, rn, true, 0);
case 0x1d:
@@ -252,6 +252,7 @@ def format ArmSyncMem() {{
"ldrex" : "LDREX_" + loadImmClassName(False, True, False, size=4),
"ldrexb" : "LDREXB_" + loadImmClassName(False, True, False, size=1),
"ldrexh" : "LDREXH_" + loadImmClassName(False, True, False, size=2),
+ "ldrexd" : "LDREXD_" + loadDoubleImmClassName(False, True, False),
"strex" : "STREX_" + storeImmClassName(False, True, False, size=4),
"strexb" : "STREXB_" + storeImmClassName(False, True, False, size=1),
"strexh" : "STREXH_" + storeImmClassName(False, True, False, size=2),