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authorAndreas Sandberg <andreas.sandberg@arm.com>2018-05-16 16:18:00 +0100
committerAndreas Sandberg <andreas.sandberg@arm.com>2018-06-06 13:56:18 +0000
commit353348d6b23572576e98c419c3ed9c1cb9bdf5e0 (patch)
treea4dad7f30aa36b773a372e9ac541fb5200dbfc47 /src/arch
parent072f325b2b5686d2a5b19f17f808810d5afd1944 (diff)
downloadgem5-353348d6b23572576e98c419c3ed9c1cb9bdf5e0.tar.xz
arch-arm: Perform stage 2 lookups using the EL2 state
Change-Id: Ic56b694f22a26e9c208a10e5703d4b5b0900070f Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10507 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/stage2_lookup.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/stage2_lookup.cc b/src/arch/arm/stage2_lookup.cc
index 00c515df5..7e78a3193 100644
--- a/src/arch/arm/stage2_lookup.cc
+++ b/src/arch/arm/stage2_lookup.cc
@@ -66,7 +66,7 @@ Stage2LookUp::getTe(ThreadContext *tc, TlbEntry *destTe)
// checking. So call translate on stage 2 to do the checking. As the
// entry is now in the TLB this should always hit the cache.
if (fault == NoFault) {
- if (inAArch64(tc))
+ if (ELIs64(tc, EL2))
fault = stage2Tlb->checkPermissions64(stage2Te, &req, mode, tc);
else
fault = stage2Tlb->checkPermissions(stage2Te, &req, mode);