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authorGiacomo Travaglini <giacomo.travaglini@arm.com>2018-02-09 11:31:05 +0000
committerGiacomo Travaglini <giacomo.travaglini@arm.com>2018-03-14 10:33:48 +0000
commit74305fad328ad22fa3bf32b50ad683043494803c (patch)
tree19603112864ba2e14fb51697b8550bb34f948e5b /src/arch
parent8dc266490de6abd2cef420b41aa0430dd2dcdd9b (diff)
downloadgem5-74305fad328ad22fa3bf32b50ad683043494803c.tar.xz
arch-arm: ERET from AArch64 to AArch32 ignore MSBs
The 32 most significant bits of ELR_ELx must be ignored when returning from AArch64 to AArch32. Change-Id: I412d72908997916404e16e9eeca2789a9c529e58 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8881 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/isa/insts/branch64.isa21
1 files changed, 14 insertions, 7 deletions
diff --git a/src/arch/arm/isa/insts/branch64.isa b/src/arch/arm/isa/insts/branch64.isa
index 64457b8c0..8ef9f934e 100644
--- a/src/arch/arm/isa/insts/branch64.isa
+++ b/src/arch/arm/isa/insts/branch64.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2011-2013, 2016 ARM Limited
+// Copyright (c) 2011-2013, 2016,2018 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -120,12 +120,19 @@ let {{
mnemonic);
break;
}
- if (spsr.width && (newPc & mask(2))) {
- // To avoid PC Alignment fault when returning to AArch32
- if (spsr.t)
- newPc = newPc & ~mask(1);
- else
- newPc = newPc & ~mask(2);
+ if (spsr.width) {
+ // Exception return to AArch32.
+ // 32 most significant bits are ignored
+ newPc &= mask(32);
+
+ if (newPc & mask(2)) {
+ // Mask bits to avoid PC Alignment fault when returning
+ // to AArch32
+ if (spsr.t)
+ newPc = newPc & ~mask(1);
+ else
+ newPc = newPc & ~mask(2);
+ }
}
CPSR new_cpsr = getPSTATEFromPSR(xc->tcBase(), cpsr, spsr);