summaryrefslogtreecommitdiff
path: root/src/arch
diff options
context:
space:
mode:
authorChuan Zhu <chuan.zhu@arm.com>2018-01-17 10:59:30 +0000
committerGiacomo Travaglini <giacomo.travaglini@arm.com>2018-04-18 15:23:07 +0000
commit8dabce896aca604f7e47a826970434b8a33b7e9d (patch)
tree59807a826831892b78a71e2063c3ac16a2343ff4 /src/arch
parentabbe32b6acacb22761e969b716631c5f616f3229 (diff)
downloadgem5-8dabce896aca604f7e47a826970434b8a33b7e9d.tar.xz
arch-arm: Fix masking in CPACR_EL1
Some bits in CPACR_EL1 are RES0 but not RAZ/WI. For instance, bit CPACR_EL1[31] is RES0 but should be made stateful, since it allows programing of CPACR.ASEDIS. Therefore the masking of CPACR_EL1 is removed. Change-Id: If1fa3fa1e06bc38495b8afce2c635f3ddf76ce32 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10046 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/isa.cc11
1 files changed, 0 insertions, 11 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 954375374..7f0e0f42b 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -754,17 +754,6 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
miscRegName[misc_reg], newVal);
}
break;
- case MISCREG_CPACR_EL1:
- {
- const uint32_t ones = (uint32_t)(-1);
- CPACR cpacrMask = 0;
- cpacrMask.tta = ones;
- cpacrMask.fpen = ones;
- newVal &= cpacrMask;
- DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
- miscRegName[misc_reg], newVal);
- }
- break;
case MISCREG_CPTR_EL2:
{
const uint32_t ones = (uint32_t)(-1);