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authorMatt Sinclair <mattdsinclair@gmail.com>2018-05-04 01:53:07 -0400
committerMatt Sinclair <mattdsinclair@gmail.com>2018-05-08 21:53:00 +0000
commitc1a2905aa22a7f46a50cb9b86a265923d6af341b (patch)
tree139409e59a6831bb0ca2756273d4a0d4282ec4c1 /src/arch
parent0b0629cda6cbb4fdc1c1087c762c27c426e8a1c9 (diff)
downloadgem5-c1a2905aa22a7f46a50cb9b86a265923d6af341b.tar.xz
arch-x86, arch-power: fix calls to bits and insertBits
The bits and insertBits assume the first bit is the larger bit and the last bit is the smaller bit. This commit fixes several X86 and Power calls to these functions that incorrectly assumed that first was the smaller bit. Change-Id: I2b5354d1b9ca66e3436c4a72042416a6ce6dec01 Reviewed-on: https://gem5-review.googlesource.com/10241 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/power/isa/decoder.isa8
-rw-r--r--src/arch/x86/isa.cc2
2 files changed, 5 insertions, 5 deletions
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 71ef95b06..6bc19adb9 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -158,8 +158,8 @@ decode OPCODE default Unknown::unknown() {
508: cmpb({{
uint32_t val = 0;
for (int n = 0; n < 32; n += 8) {
- if(bits(Rs, n, n+7) == bits(Rb, n, n+7)) {
- val = insertBits(val, n, n+7, 0xff);
+ if(bits(Rs, n+7, n) == bits(Rb, n+7, n)) {
+ val = insertBits(val, n+7, n, 0xff);
}
}
Ra = val;
@@ -580,8 +580,8 @@ decode OPCODE default Unknown::unknown() {
for (int i = 0; i < 8; ++i) {
if (bits(FLM, i) == 1) {
int k = 4 * (i + (8 * (1 - W_FIELD)));
- FPSCR = insertBits(FPSCR, k, k + 3,
- bits(Fb_uq, k, k + 3));
+ FPSCR = insertBits(FPSCR, k + 3, k,
+ bits(Fb_uq, k + 3, k));
}
}
}
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index 28c50f358..a866b950f 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -145,7 +145,7 @@ ISA::readMiscReg(int miscReg, ThreadContext * tc)
if (miscReg == MISCREG_FSW) {
MiscReg fsw = regVal[MISCREG_FSW];
MiscReg top = regVal[MISCREG_X87_TOP];
- return insertBits(fsw, 11, 13, top);
+ return insertBits(fsw, 13, 11, top);
}
return readMiscRegNoEffect(miscReg);