diff options
author | Gabe Black <gblack@eecs.umich.edu> | 2007-07-20 15:04:41 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2007-07-20 15:04:41 -0700 |
commit | dfcb2ffa462c37497579bd2bab88af8ba09c3f56 (patch) | |
tree | dcc355fd1a362b2c855c5d438d1f2d237d673f61 /src/arch | |
parent | fcc23891bbfd06cff9d3f486a6c73eb9d159aa07 (diff) | |
download | gem5-dfcb2ffa462c37497579bd2bab88af8ba09c3f56.tar.xz |
Comment, implement, fix, and trim the move microassembly.
--HG--
extra : convert_revision : aa5ee7270e740bfbe42e70c4dfccc4c91ecacb33
Diffstat (limited to 'src/arch')
-rw-r--r-- | src/arch/x86/isa/insts/data_transfer/move.py | 89 |
1 files changed, 52 insertions, 37 deletions
diff --git a/src/arch/x86/isa/insts/data_transfer/move.py b/src/arch/x86/isa/insts/data_transfer/move.py index 9856b5051..bbc55e47c 100644 --- a/src/arch/x86/isa/insts/data_transfer/move.py +++ b/src/arch/x86/isa/insts/data_transfer/move.py @@ -54,6 +54,11 @@ # Authors: Gabe Black microcode = ''' + +# +# Regular moves +# + def macroop MOV_R_R { mov reg, reg, regm }; @@ -91,77 +96,87 @@ def macroop MOV_P_I { st t1, ds, [0, t0, t7], disp }; +# +# Sign extending moves +# + def macroop MOVSXD_R_R { - sext reg, regm, dsz + sext reg, regm, 32 }; def macroop MOVSXD_R_M { - ld t1, ds, [scale, index, base], disp - sext reg, t1, dsz + ld t1, ds, [scale, index, base], disp, dataSize=4 + sext reg, t1, 32 }; def macroop MOVSXD_R_P { rdip t7 - ld t1, ds, [0, t0, t7], disp - sext reg, t1, dsz + ld t1, ds, [0, t0, t7], disp, dataSize=4 + sext reg, t1, 32 }; -def macroop MOVZX_B_R_R { - mov reg, reg, t0 - mov reg, reg, regm, dataSize=1 +def macroop MOVSX_B_R_R { + sext reg, regm, 8 }; -def macroop MOVZX_B_R_M { - mov reg, reg, t0 +def macroop MOVSX_B_R_M { ld reg, ds, [scale, index, base], disp, dataSize=1 + sext reg, reg, 8 }; -def macroop MOVZX_B_R_P { +def macroop MOVSX_B_R_P { rdip t7 - mov reg, reg, t0 ld reg, ds, [0, t0, t7], disp, dataSize=1 + sext reg, reg, 8 }; -def macroop MOVZX_B_M_R { - mov t1, t1, t0 - mov t1, t1, reg, dataSize=1 - st t1, ds, [scale, index, base], disp +def macroop MOVSX_W_R_R { + sext reg, regm, 16 +}; + +def macroop MOVSX_W_R_M { + ld reg, ds, [scale, index, base], disp, dataSize=2 + sext reg, reg, 16 }; -def macroop MOVZX_B_P_R { +def macroop MOVSX_W_R_P { rdip t7 - mov t1, t1, t0 - mov t1, t1, reg, dataSize=1 - st t1, ds, [0, t0, t7], disp + ld reg, ds, [0, t0, t7], disp, dataSize=2 + sext reg, reg, 16 }; -def macroop MOVZX_W_R_R { - mov reg, reg, t0 - mov reg, reg, regm, dataSize=2 +# +# Zero extending moves +# + +def macroop MOVZX_B_R_R { + zext reg, regm, 8 }; -def macroop MOVZX_W_R_M { - mov reg, reg, t0 - ld reg, ds, [scale, index, base], disp, dataSize=2 +def macroop MOVZX_B_R_M { + ld t1, ds, [scale, index, base], disp, dataSize=1 + zext reg, t1, 8 }; -def macroop MOVZX_W_R_P { +def macroop MOVZX_B_R_P { rdip t7 - mov reg, reg, t0 - ld reg, ds, [0, t0, t7], disp, dataSize=2 + ld t1, ds, [0, t0, t7], disp, dataSize=1 + zext reg, t1, 8 }; -def macroop MOVZX_W_M_R { - mov t1, t1, t0 - mov t1, t1, reg, dataSize=2 - st t1, ds, [scale, index, base], disp +def macroop MOVZX_W_R_R { + zext reg, regm, 16 +}; + +def macroop MOVZX_W_R_M { + ld t1, ds, [scale, index, base], disp, dataSize=2 + zext reg, t1, 16 }; -def macroop MOVZX_W_P_R { +def macroop MOVZX_W_R_P { rdip t7 - mov t1, t1, t0 - mov t1, t1, reg, dataSize=2 - st t1, ds, [0, t0, t7], disp + ld t1, ds, [0, t0, t7], disp, dataSize=2 + zext reg, t1, 16 }; ''' #let {{ |