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author | Ali Saidi <saidi@eecs.umich.edu> | 2006-08-15 17:41:22 -0400 |
---|---|---|
committer | Ali Saidi <saidi@eecs.umich.edu> | 2006-08-15 17:41:22 -0400 |
commit | ed58f77c473cf6f35a17ba1448a12dbca089987d (patch) | |
tree | 00b9ecfc881086d1ceaa5e62073b1bb979fa6837 /src/arch | |
parent | 07488510713a1df61f6cefced7677047cfc0ef66 (diff) | |
download | gem5-ed58f77c473cf6f35a17ba1448a12dbca089987d.tar.xz |
fixes for gcc 4.1
Nate needs to fix sinic builder stuff
Gabe needs to verify my fixes to decoder.isa
OPT/DEBUG compiles for ALPHA_FS, ALPHA_SE, MIPS_SE, SPARC_SE with this changeset
README:
Fix the swig version in the readme
src/SConscript:
remove sinic until nate fixes the builder crap for it
src/arch/alpha/system.hh:
src/arch/mips/isa/includes.isa:
src/arch/sparc/isa/decoder.isa:
src/base/stats/visit.cc:
src/base/timebuf.hh:
src/dev/ide_disk.cc:
src/dev/sinic.cc:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr_queue.cc:
src/mem/packet.hh:
src/mem/request.hh:
src/sim/builder.hh:
src/sim/system.hh:
fixes for gcc 4.1
--HG--
extra : convert_revision : 3775427c0047b282574d4831dd602c96cac3ba17
Diffstat (limited to 'src/arch')
-rw-r--r-- | src/arch/alpha/system.hh | 4 | ||||
-rw-r--r-- | src/arch/mips/isa/includes.isa | 1 | ||||
-rw-r--r-- | src/arch/sparc/isa/decoder.isa | 8 |
3 files changed, 7 insertions, 6 deletions
diff --git a/src/arch/alpha/system.hh b/src/arch/alpha/system.hh index 0f4f64581..0c073a68c 100644 --- a/src/arch/alpha/system.hh +++ b/src/arch/alpha/system.hh @@ -91,14 +91,14 @@ class AlphaSystem : public System /** Add a function-based event to PALcode. */ template <class T> - T *AlphaSystem::addPalFuncEvent(const char *lbl) + T *addPalFuncEvent(const char *lbl) { return addFuncEvent<T>(palSymtab, lbl); } /** Add a function-based event to the console code. */ template <class T> - T *AlphaSystem::addConsoleFuncEvent(const char *lbl) + T *addConsoleFuncEvent(const char *lbl) { return addFuncEvent<T>(consoleSymtab, lbl); } diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa index 6b5f3c588..f58c8adaa 100644 --- a/src/arch/mips/isa/includes.isa +++ b/src/arch/mips/isa/includes.isa @@ -75,6 +75,7 @@ output exec {{ #include "cpu/base.hh" #include "cpu/exetrace.hh" #include "sim/sim_exit.hh" +#include "mem/packet_impl.hh" using namespace MipsISA; }}; diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index 0c2729833..25203f45c 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -220,7 +220,7 @@ decode OP default Unknown::unknown() ,{{0}},{{0}},{{0}},{{0}}); 0x1E: udivcc({{ uint32_t resTemp, val2 = Rs2_or_imm13.udw; - int32_t overflow; + int32_t overflow = 0; if(val2 == 0) fault = new DivisionByZero; else { @@ -236,7 +236,7 @@ decode OP default Unknown::unknown() ); 0x1F: sdivcc({{ int32_t resTemp, val2 = Rs2_or_imm13.sdw; - int32_t overflow, underflow; + int32_t overflow = 0, underflow = 0; if(val2 == 0) fault = new DivisionByZero; else { @@ -244,7 +244,7 @@ decode OP default Unknown::unknown() overflow = (resTemp<63:31> != 0); underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF); if(overflow) Rd = resTemp = 0x7FFFFFFF; - else if(underflow) Rd = resTemp = 0xFFFFFFFF80000000ULL; + else if(underflow) resTemp = Rd = 0xFFFFFFFF80000000ULL; else Rd = resTemp; } }}, {{0}}, @@ -272,7 +272,7 @@ decode OP default Unknown::unknown() ); 0x22: taddcctv({{ int64_t resTemp, val2 = Rs2_or_imm13; - Rd = Rs1 + val2; + Rd = resTemp = Rs1 + val2; int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>); if(overflow) fault = new TagOverflow;}}, |