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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:12 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:12 -0500
commit186cfe3ae30970b43c09cccab6f004ea7d720838 (patch)
treeefa4ffda369318c20c4930ad439bd8d28e6f89d4 /src/arch
parentb87ebf382f1c53b1b8ae58fc86d82dcc22d882d8 (diff)
downloadgem5-186cfe3ae30970b43c09cccab6f004ea7d720838.tar.xz
ARM: Widen the immediate fields in the misc instruction classes.
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/insts/misc.hh22
-rw-r--r--src/arch/arm/isa/templates/misc.isa22
2 files changed, 22 insertions, 22 deletions
diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh
index 8080c4e1f..79cec5732 100644
--- a/src/arch/arm/insts/misc.hh
+++ b/src/arch/arm/insts/misc.hh
@@ -97,10 +97,10 @@ class MsrRegOp : public MsrBase
class ImmOp : public PredOp
{
protected:
- uint32_t imm;
+ uint64_t imm;
ImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- uint32_t _imm) :
+ uint64_t _imm) :
PredOp(mnem, _machInst, __opClass), imm(_imm)
{}
@@ -125,11 +125,11 @@ class RegImmRegOp : public PredOp
{
protected:
IntRegIndex dest;
- uint32_t imm;
+ uint64_t imm;
IntRegIndex op1;
RegImmRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, uint32_t _imm, IntRegIndex _op1) :
+ IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1) :
PredOp(mnem, _machInst, __opClass),
dest(_dest), imm(_imm), op1(_op1)
{}
@@ -143,11 +143,11 @@ class RegRegRegImmOp : public PredOp
IntRegIndex dest;
IntRegIndex op1;
IntRegIndex op2;
- uint32_t imm;
+ uint64_t imm;
RegRegRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
- uint32_t _imm) :
+ uint64_t _imm) :
PredOp(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2), imm(_imm)
{}
@@ -194,12 +194,12 @@ class RegRegImmImmOp : public PredOp
protected:
IntRegIndex dest;
IntRegIndex op1;
- uint32_t imm1;
- uint32_t imm2;
+ uint64_t imm1;
+ uint64_t imm2;
RegRegImmImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
IntRegIndex _dest, IntRegIndex _op1,
- uint32_t _imm1, uint32_t _imm2) :
+ uint64_t _imm1, uint64_t _imm2) :
PredOp(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2)
{}
@@ -211,13 +211,13 @@ class RegImmRegShiftOp : public PredOp
{
protected:
IntRegIndex dest;
- uint32_t imm;
+ uint64_t imm;
IntRegIndex op1;
int32_t shiftAmt;
ArmShiftType shiftType;
RegImmRegShiftOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, uint32_t _imm, IntRegIndex _op1,
+ IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1,
int32_t _shiftAmt, ArmShiftType _shiftType) :
PredOp(mnem, _machInst, __opClass),
dest(_dest), imm(_imm), op1(_op1),
diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa
index 771b6d784..e880b03ec 100644
--- a/src/arch/arm/isa/templates/misc.isa
+++ b/src/arch/arm/isa/templates/misc.isa
@@ -105,13 +105,13 @@ class %(class_name)s : public %(base_class)s
protected:
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, uint32_t _imm);
+ %(class_name)s(ExtMachInst machInst, uint64_t _imm);
%(BasicExecDeclare)s
};
}};
def template ImmOpConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _imm)
+ inline %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm)
{
%(constructor)s;
@@ -147,7 +147,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
- uint32_t _imm);
+ uint64_t _imm);
%(BasicExecDeclare)s
};
}};
@@ -157,7 +157,7 @@ def template RegRegRegImmOpConstructor {{
IntRegIndex _dest,
IntRegIndex _op1,
IntRegIndex _op2,
- uint32_t _imm)
+ uint64_t _imm)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _imm)
{
@@ -223,7 +223,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, IntRegIndex _op1,
- uint32_t _imm1, uint32_t _imm2);
+ uint64_t _imm1, uint64_t _imm2);
%(BasicExecDeclare)s
};
}};
@@ -232,8 +232,8 @@ def template RegRegImmImmOpConstructor {{
inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest,
IntRegIndex _op1,
- uint32_t _imm1,
- uint32_t _imm2)
+ uint64_t _imm1,
+ uint64_t _imm2)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm1, _imm2)
{
@@ -248,7 +248,7 @@ class %(class_name)s : public %(base_class)s
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, uint32_t _imm, IntRegIndex _op1);
+ IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1);
%(BasicExecDeclare)s
};
}};
@@ -256,7 +256,7 @@ class %(class_name)s : public %(base_class)s
def template RegImmRegOpConstructor {{
inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest,
- uint32_t _imm,
+ uint64_t _imm,
IntRegIndex _op1)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _imm, _op1)
@@ -272,7 +272,7 @@ class %(class_name)s : public %(base_class)s
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, uint32_t _imm, IntRegIndex _op1,
+ IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1,
int32_t _shiftAmt, ArmShiftType _shiftType);
%(BasicExecDeclare)s
};
@@ -281,7 +281,7 @@ class %(class_name)s : public %(base_class)s
def template RegImmRegShiftOpConstructor {{
inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest,
- uint32_t _imm,
+ uint64_t _imm,
IntRegIndex _op1,
int32_t _shiftAmt,
ArmShiftType _shiftType)