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authorNathanael Premillieu <npremill@irisa.fr>2012-03-21 10:34:06 -0500
committerNathanael Premillieu <npremill@irisa.fr>2012-03-21 10:34:06 -0500
commit8e2a8fbb7e4751260c88fccd19ebe8d1138d0695 (patch)
tree39eaf5291e5e69e4c9f87a2affc0ab7e013c4367 /src/arch
parented8ed6e7614057e0c8f7461ea9f7a8f2d59a57ea (diff)
downloadgem5-8e2a8fbb7e4751260c88fccd19ebe8d1138d0695.tar.xz
ARM: Fix case where cond/uncond control is mis-specified
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/isa/templates/pred.isa4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa
index 8d9d16492..efb8e470b 100644
--- a/src/arch/arm/isa/templates/pred.isa
+++ b/src/arch/arm/isa/templates/pred.isa
@@ -112,9 +112,9 @@ def template DataRegConstructor {{
flags[IsControl] = true;
flags[IsIndirectControl] = true;
if (condCode == COND_AL || condCode == COND_UC)
- flags[IsCondControl] = true;
- else
flags[IsUncondControl] = true;
+ else
+ flags[IsCondControl] = true;
}
if (%(is_ras_pop)s) {