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authorBrian Grayson <b.grayson@samsung.com>2012-03-09 15:32:41 -0500
committerBrian Grayson <b.grayson@samsung.com>2012-03-09 15:32:41 -0500
commit9a9a4a0780865dc722b7564ea1c1bf8bacb4e5ce (patch)
treea1596bb344b87df16f86cb402174b077cfe09270 /src/arch
parent927bba9d605238ee3fde21ac5913c8ed5ab9fba8 (diff)
downloadgem5-9a9a4a0780865dc722b7564ea1c1bf8bacb4e5ce.tar.xz
ARM: Fix branch prediction issue with CB(N)Z instruction
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/isa/templates/branch.isa11
1 files changed, 3 insertions, 8 deletions
diff --git a/src/arch/arm/isa/templates/branch.isa b/src/arch/arm/isa/templates/branch.isa
index 3a8fbb363..6edfb0ee0 100644
--- a/src/arch/arm/isa/templates/branch.isa
+++ b/src/arch/arm/isa/templates/branch.isa
@@ -212,6 +212,8 @@ class %(class_name)s : public %(base_class)s
};
}};
+// Only used by CBNZ, CBZ which is conditional based on
+// a register value even though the instruction is always unconditional.
def template BranchImmRegConstructor {{
inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
int32_t _imm,
@@ -219,14 +221,7 @@ def template BranchImmRegConstructor {{
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1)
{
%(constructor)s;
- if (!(condCode == COND_AL || condCode == COND_UC)) {
- for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
- }
- flags[IsCondControl] = true;
- } else {
- flags[IsUncondControl] = true;
- }
+ flags[IsCondControl] = true;
}
}};