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authorAli Saidi <saidi@eecs.umich.edu>2007-01-21 20:02:41 -0500
committerAli Saidi <saidi@eecs.umich.edu>2007-01-21 20:02:41 -0500
commita7072c19dbd6273920a90a4ec5fa013531316287 (patch)
treecca18d25e06bcfda1500e98e24d310160fc9584e /src/arch
parent3af3610c625d57db3fa75af4f4b24ae72a76595f (diff)
downloadgem5-a7072c19dbd6273920a90a4ec5fa013531316287.tar.xz
make sure that page bits of VA on tlb insert are 0
--HG-- extra : convert_revision : f04af884687e9b8631e910cf62cd4a58d035c744
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/sparc/tlb.cc1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 460a9c640..61445954f 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -85,6 +85,7 @@ TLB::insert(Addr va, int partition_id, int context_id, bool real,
int x;
cacheValid = false;
+ va &= ~(PTE.size()-1);
/* tr.va = va;
tr.size = PTE.size() - 1;
tr.contextId = context_id;