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authorGabe Black <gblack@eecs.umich.edu>2006-11-14 15:23:23 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-11-14 15:23:23 -0500
commitac2c7967f69e3ffd29a1ed04a15838073dc060de (patch)
treed24dc27dcb11414775d2971b645ef4a6fbb922d9 /src/arch
parentbc4d15ddd199420d2201fd0e8bde399e51ea0d3d (diff)
parent2f6a9454d13e44faba55b14d958f20a04bc36246 (diff)
downloadgem5-ac2c7967f69e3ffd29a1ed04a15838073dc060de.tar.xz
Merge zizzer.eecs.umich.edu:/bk/newmem/
into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops --HG-- extra : convert_revision : 966246877ac1f1e6c2675d413b0b405cccfecbeb
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/alpha/interrupts.hh28
-rw-r--r--src/arch/alpha/miscregfile.cc10
-rw-r--r--src/arch/alpha/tlb.cc2
-rw-r--r--src/arch/sparc/interrupts.hh5
4 files changed, 27 insertions, 18 deletions
diff --git a/src/arch/alpha/interrupts.hh b/src/arch/alpha/interrupts.hh
index 75031ae47..a86fb2d7b 100644
--- a/src/arch/alpha/interrupts.hh
+++ b/src/arch/alpha/interrupts.hh
@@ -49,6 +49,7 @@ namespace AlphaISA
{
memset(interrupts, 0, sizeof(interrupts));
intstatus = 0;
+ newInfoSet = false;
}
void post(int int_num, int index)
@@ -137,18 +138,10 @@ namespace AlphaISA
}
if (ipl && ipl > tc->readMiscReg(IPR_IPLR)) {
- tc->setMiscReg(IPR_ISR, summary);
- tc->setMiscReg(IPR_INTID, ipl);
-
- /* The following needs to be added back in somehow */
- // Checker needs to know these two registers were updated.
-/*#if USE_CHECKER
- if (this->checker) {
- this->checker->threadBase()->setMiscReg(IPR_ISR, summary);
- this->checker->threadBase()->setMiscReg(IPR_INTID, ipl);
- }
-#endif*/
-
+// assert(!newInfoSet);
+ newIpl = ipl;
+ newSummary = newSummary;
+ newInfoSet = true;
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
tc->readMiscReg(IPR_IPLR), ipl, summary);
@@ -158,7 +151,18 @@ namespace AlphaISA
}
}
+ void updateIntrInfo(ThreadContext *tc)
+ {
+ assert(newInfoSet);
+ tc->setMiscReg(IPR_ISR, newSummary);
+ tc->setMiscReg(IPR_INTID, newIpl);
+ newInfoSet = false;
+ }
+
private:
+ bool newInfoSet;
+ int newIpl;
+ int newSummary;
};
}
diff --git a/src/arch/alpha/miscregfile.cc b/src/arch/alpha/miscregfile.cc
index 4cf57a690..962d4609f 100644
--- a/src/arch/alpha/miscregfile.cc
+++ b/src/arch/alpha/miscregfile.cc
@@ -132,7 +132,6 @@ namespace AlphaISA
MiscRegFile::setRegWithEffect(int misc_reg, const MiscReg &val,
ThreadContext *tc)
{
-#if FULL_SYSTEM
switch(misc_reg) {
case MISCREG_FPCR:
fpcr = val;
@@ -150,12 +149,13 @@ namespace AlphaISA
intr_flag = val;
return;
default:
- return setIpr(misc_reg, val, tc);
- }
+#if FULL_SYSTEM
+ setIpr(misc_reg, val, tc);
#else
- //panic("No registers with side effects in SE mode!");
- return;
+ panic("No registers with side effects in SE mode!");
#endif
+ return;
+ }
}
}
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index ae302e686..af69e45c0 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -292,7 +292,7 @@ namespace AlphaISA
Fault
ITB::translate(RequestPtr &req, ThreadContext *tc) const
{
- if (PcPAL(req->getVaddr())) {
+ if (PcPAL(req->getPC())) {
// strip off PAL PC marker (lsb is 1)
req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask);
hits++;
diff --git a/src/arch/sparc/interrupts.hh b/src/arch/sparc/interrupts.hh
index 0072f4184..70838d1ce 100644
--- a/src/arch/sparc/interrupts.hh
+++ b/src/arch/sparc/interrupts.hh
@@ -79,6 +79,11 @@ namespace SparcISA
return NoFault;
}
+ void updateIntrInfo(ThreadContext * tc)
+ {
+
+ }
+
void serialize(std::ostream &os)
{
}