Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions.

9 files changed, 0 insertions, 89 deletions

diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 3bc0492b1..bf641d2fe 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -127,18 +127,6 @@ zeroRegisters(CPU *cpu)
     cpu->thread->setFloatReg(ZeroReg, 0.0);
 }
 
-int
-ISA::getInstAsid()
-{
-    return ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
-}
-
-int
-ISA::getDataAsid()
-{
-    return DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
-}
-
 #endif
 
 ////////////////////////////////////////////////////////////////////////
diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh
index dbd1c43a9..622d1da4c 100644
--- a/src/arch/alpha/isa.hh
+++ b/src/arch/alpha/isa.hh
@@ -65,11 +65,6 @@ namespace AlphaISA
 
       public:
 
-        // These functions should be removed once the simplescalar cpu
-        // model has been replaced.
-        int getInstAsid();
-        int getDataAsid();
-
         MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
         MiscReg readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
 
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index 7380ad9f9..252c788a8 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -57,16 +57,6 @@ namespace MipsISA
             miscRegFile.reset(core_name, num_threads, num_vpes, _cpu);
         }
 
-        int instAsid()
-        {
-            return miscRegFile.getInstAsid();
-        }
-
-        int dataAsid()
-        {
-            return miscRegFile.getDataAsid();
-        }
-
         void clear();
 
         MiscReg readMiscRegNoEffect(int miscReg);
diff --git a/src/arch/mips/mips_core_specific.cc b/src/arch/mips/mips_core_specific.cc
index 80d856b0c..21847378f 100755
--- a/src/arch/mips/mips_core_specific.cc
+++ b/src/arch/mips/mips_core_specific.cc
@@ -109,19 +109,4 @@ MipsISA::processInterrupts(CPU *cpu)
   */
 }
 
-
-/*int
-MipsISA::MiscRegFile::getInstAsid()
-{
-    return AlphaISA::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
-}
-
-int
-MipsISA::MiscRegFile::getDataAsid()
-{
-    return AlphaISA::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
-    }*/
-
-
-
 #endif // FULL_SYSTEM || BARE_IRON
diff --git a/src/arch/mips/misc_regfile.cc b/src/arch/mips/misc_regfile.cc
index bb4a361f7..da35dc668 100644
--- a/src/arch/mips/misc_regfile.cc
+++ b/src/arch/mips/misc_regfile.cc
@@ -167,17 +167,6 @@ MiscRegFile::expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
     }
 
 }
-int MiscRegFile::getInstAsid()
-{
-  MiscReg Entry_Hi = readRegNoEffect(EntryHi);
-  return bits(Entry_Hi,EntryHi_ASID_HI,EntryHi_ASID_LO);
-}
-
-int MiscRegFile:: getDataAsid()
-{
-  MiscReg EHi = readRegNoEffect(EntryHi);
-  return bits(EHi,EntryHi_ASID_HI,EntryHi_ASID_LO);
-}
 //@TODO: Use MIPS STYLE CONSTANTS (e.g. TCHALT_H instead of TCH_H)
 void
 MiscRegFile::reset(std::string core_name, ThreadID num_threads,
diff --git a/src/arch/mips/misc_regfile.hh b/src/arch/mips/misc_regfile.hh
index ab233abde..4983feb88 100644
--- a/src/arch/mips/misc_regfile.hh
+++ b/src/arch/mips/misc_regfile.hh
@@ -103,9 +103,6 @@ namespace MipsISA
         void setReg(int misc_reg, const MiscReg &val,
                      ThreadContext *tc, ThreadID tid = 0);
 
-        int getInstAsid();
-        int getDataAsid();
-
         //////////////////////////////////////////////////////////
         //
         // DECLARE INTERFACE THAT WILL ALLOW A MiscRegFile (Cop0)
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index 1dbfe7a28..bba578ef1 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -45,17 +45,6 @@ namespace SparcISA
         MiscRegFile miscRegFile;
 
       public:
-
-        int instAsid()
-        {
-            return miscRegFile.getInstAsid();
-        }
-
-        int dataAsid()
-        {
-            return miscRegFile.getDataAsid();
-        }
-
         void clear();
 
         MiscReg readMiscRegNoEffect(int miscReg);
diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh
index c6ba27b93..36c309db2 100644
--- a/src/arch/sparc/miscregfile.hh
+++ b/src/arch/sparc/miscregfile.hh
@@ -158,16 +158,6 @@ namespace SparcISA
         void setReg(int miscReg,
                 const MiscReg &val, ThreadContext * tc);
 
-        int getInstAsid()
-        {
-            return priContext | (uint32_t)partId << 13;
-        }
-
-        int getDataAsid()
-        {
-            return priContext | (uint32_t)partId << 13;
-        }
-
         void serialize(EventManager *em, std::ostream & os);
 
         void unserialize(EventManager *em, Checkpoint *cp,
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index 34c803f0c..5b120d69e 100644
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -45,18 +45,6 @@ namespace X86ISA
         MiscRegFile miscRegFile;
 
       public:
-        int instAsid()
-        {
-            //XXX This doesn't make sense in x86
-            return 0;
-        }
-
-        int dataAsid()
-        {
-            //XXX This doesn't make sense in x86
-            return 0;
-        }
-
         void clear();
 
         MiscReg readMiscRegNoEffect(int miscReg);