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authorGene Wu <Gene.Wu@arm.com>2010-08-23 11:18:41 -0500
committerGene Wu <Gene.Wu@arm.com>2010-08-23 11:18:41 -0500
commitd6736384b2bb280ec12d472cac6eb25a70b4af60 (patch)
tree4ab72a9724a1f349a6c9ddc3088e73d7cebd7f90 /src/arch
parent23626d99af9469b5a86f510e0542846f5af65cbd (diff)
downloadgem5-d6736384b2bb280ec12d472cac6eb25a70b4af60.tar.xz
MEM: Make CLREX a first class request operation and clear locks in caches when it in received
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/isa/insts/misc.isa2
-rw-r--r--src/arch/arm/isa/templates/misc.isa2
-rw-r--r--src/arch/arm/tlb.cc3
-rw-r--r--src/arch/arm/tlb.hh3
4 files changed, 5 insertions, 5 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 2228a0f24..33197eaec 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -669,7 +669,7 @@ let {{
exec_output += PredOpExecute.subst(setendIop)
clrexCode = '''
- unsigned memAccessFlags = ArmISA::TLB::Clrex|3|Request::LLSC;
+ unsigned memAccessFlags = Request::CLREX|3|Request::LLSC;
fault = xc->read(0, (uint32_t&)Mem, memAccessFlags);
'''
clrexIop = InstObjParams("clrex", "Clrex","PredOp",
diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa
index d2224dc6d..46af3f5b1 100644
--- a/src/arch/arm/isa/templates/misc.isa
+++ b/src/arch/arm/isa/templates/misc.isa
@@ -367,7 +367,7 @@ def template ClrexInitiateAcc {{
if (%(predicate_test)s)
{
if (fault == NoFault) {
- unsigned memAccessFlags = ArmISA::TLB::Clrex|3|Request::LLSC;
+ unsigned memAccessFlags = Request::CLREX|3|Request::LLSC;
fault = xc->read(0, (uint32_t&)Mem, memAccessFlags);
}
} else {
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index a70a20518..a48805c81 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -358,9 +358,10 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
// If this is a clrex instruction, provide a PA of 0 with no fault
// This will force the monitor to set the tracked address to 0
// a bit of a hack but this effectively clrears this processors monitor
- if (flags & Clrex){
+ if (flags & Request::CLREX){
req->setPaddr(0);
req->setFlags(Request::UNCACHEABLE);
+ req->setFlags(Request::CLREX);
return NoFault;
}
if ((req->isInstFetch() && (!sctlr.i)) ||
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index d1ba42b39..1bddd8497 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -78,8 +78,7 @@ class TLB : public BaseTLB
// Because zero otherwise looks like a valid setting and may be used
// accidentally, this bit must be non-zero to show it was used on
// purpose.
- MustBeOne = 0x20,
- Clrex = 0x40
+ MustBeOne = 0x20
};
protected:
typedef std::multimap<Addr, int> PageTable;