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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:13 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:13 -0500
commiteac239b4d6f6d9eccb3837330e3f22acefc1b48e (patch)
tree7d320f4db0aeab18124240fd11ca183dbcaab53e /src/arch
parent9fb573d91e96f06505311462d902300b72b4b9a0 (diff)
downloadgem5-eac239b4d6f6d9eccb3837330e3f22acefc1b48e.tar.xz
ARM: Handle accesses to TLBTR.
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/isa.hh5
-rw-r--r--src/arch/arm/miscregs.hh4
2 files changed, 7 insertions, 2 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index f4ff58a28..41382e510 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -131,6 +131,9 @@ namespace ArmISA
(0 << 0) | //Revision
0;
+ // Separate Instruction and Data TLBs.
+ miscRegs[MISCREG_TLBTR] = 1;
+
//XXX We need to initialize the rest of the state.
}
@@ -269,6 +272,8 @@ namespace ArmISA
case MISCREG_CSSELR:
warn("The csselr register isn't implemented.\n");
break;
+ case MISCREG_TLBTR:
+ return;
}
return setMiscRegNoEffect(misc_reg, newVal);
}
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 6d8c32845..eac842307 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -108,10 +108,10 @@ namespace ArmISA
MISCREG_MIDR,
MISCREG_TTBR0,
MISCREG_TTBR1,
+ MISCREG_TLBTR,
MISCREG_DACR,
MISCREG_CP15_UNIMP_START,
MISCREG_CTR = MISCREG_CP15_UNIMP_START,
- MISCREG_TLBTR,
MISCREG_TCMTR,
MISCREG_MPIDR,
MISCREG_ID_PFR0,
@@ -198,7 +198,7 @@ namespace ArmISA
"clidr", "ccsidr", "csselr",
"icialluis", "iciallu", "icimvau",
"bpimva", "bpiallis", "bpiall",
- "midr", "ttbr0", "ttbr1", "dacr", "ctr", "tlbtr", "tcmtr", "mpidr",
+ "midr", "ttbr0", "ttbr1", "tlbtr", "dacr", "ctr", "tcmtr", "mpidr",
"id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
"id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",