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authorAndreas Sandberg <Andreas.Sandberg@ARM.com>2013-01-07 13:05:44 -0500
committerAndreas Sandberg <Andreas.Sandberg@ARM.com>2013-01-07 13:05:44 -0500
commit38925ff62126e43ea3d44ace39d908ba38dfc1af (patch)
tree8c0b37285a3751181aa69f470eb09421f6fc8c5d /src/arch
parenta7e0cbeb36394eec3960dc0e2fb15377880e9e98 (diff)
downloadgem5-38925ff62126e43ea3d44ace39d908ba38dfc1af.tar.xz
arm: Remove the register mapping hack used when copying TCs
In order to see all registers independent of the current CPU mode, the ARM architecture model uses the magic MISCREG_CPSR_MODE register to change the register mappings without actually updating the CPU mode. This hack is no longer needed since the thread context now provides a flat interface to the register file. This patch replaces the CPSR_MODE hack with the flat register interface.
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/isa.cc7
-rw-r--r--src/arch/arm/miscregs.hh3
-rw-r--r--src/arch/arm/utility.cc24
3 files changed, 7 insertions, 27 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 99acbb4fd..117873450 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -654,13 +654,6 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
tc->getITBPtr()->invalidateMiscReg();
tc->getDTBPtr()->invalidateMiscReg();
break;
- case MISCREG_CPSR_MODE:
- // This miscreg is used by copy*Regs to set the CPSR mode
- // without updating other CPSR variables. It's used to
- // make sure the register map is in such a state that we can
- // see all of the registers for the copy.
- updateRegMap(val);
- return;
case MISCREG_L2CTLR:
warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
miscRegName[misc_reg], uint32_t(val));
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 2dceab70c..02c03a7fc 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -209,7 +209,6 @@ namespace ArmISA
MISCREG_ID_ISAR3,
MISCREG_ID_ISAR4,
MISCREG_ID_ISAR5,
- MISCREG_CPSR_MODE,
MISCREG_LOCKFLAG,
MISCREG_LOCKADDR,
MISCREG_ID_PFR1,
@@ -311,7 +310,7 @@ namespace ArmISA
"pmceid1", "pmc_other", "pmxevcntr",
"pmuserenr", "pmintenset", "pmintenclr",
"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
- "cpsr_mode", "lockflag", "lockaddr", "id_pfr1",
+ "lockflag", "lockaddr", "id_pfr1",
"l2ctlr",
// Unimplemented below
"tcmtr",
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 71ad21e1e..776c1ae82 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2009-2010 ARM Limited
+ * Copyright (c) 2009-2012 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -127,25 +127,13 @@ skipFunction(ThreadContext *tc)
void
copyRegs(ThreadContext *src, ThreadContext *dest)
{
- int i;
+ for (int i = 0; i < TheISA::NumIntRegs; i++)
+ dest->setIntRegFlat(i, src->readIntRegFlat(i));
- int saved_mode = ((CPSR)src->readMiscReg(MISCREG_CPSR)).mode;
+ for (int i = 0; i < TheISA::NumFloatRegs; i++)
+ dest->setFloatRegFlat(i, src->readFloatRegFlat(i));
- // Make sure we're in user mode, so we can easily see all the registers
- // in the copy loop
- src->setMiscReg(MISCREG_CPSR_MODE, MODE_USER);
- dest->setMiscReg(MISCREG_CPSR_MODE, MODE_USER);
-
- for(i = 0; i < TheISA::NumIntRegs; i++)
- dest->setIntReg(i, src->readIntReg(i));
-
- // Restore us back to the old mode
- src->setMiscReg(MISCREG_CPSR_MODE, saved_mode);
- dest->setMiscReg(MISCREG_CPSR_MODE, saved_mode);
-
- for(i = 0; i < TheISA::NumFloatRegs; i++)
- dest->setFloatReg(i, src->readFloatReg(i));
- for(i = 0; i < TheISA::NumMiscRegs; i++)
+ for (int i = 0; i < TheISA::NumMiscRegs; i++)
dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
// setMiscReg "with effect" will set the misc register mapping correctly.