X86: Get X86_FS to compile.

--HG--
extra : convert_revision : fb973bcf13648876d5691231845dd47a2be50f01

12 files changed, 636 insertions, 4 deletions

diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript
index b3fd67f89..f4a8782f2 100644
--- a/src/arch/x86/SConscript
+++ b/src/arch/x86/SConscript
@@ -105,7 +105,9 @@ if env['TARGET_ISA'] == 'x86':
 
     if env['FULL_SYSTEM']:
         # Full-system sources
-        pass
+        Source('stacktrace.cc')
+        Source('utility.cc')
+        Source('vtophys.cc')
     else:
         Source('process.cc')
 
diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh
index 3f33b8d85..614909f73 100644
--- a/src/arch/x86/interrupts.hh
+++ b/src/arch/x86/interrupts.hh
@@ -58,10 +58,75 @@
 #ifndef __ARCH_X86_INTERRUPTS_HH__
 #define __ARCH_X86_INTERRUPTS_HH__
 
-#error X86 is not yet supported!
+#include "arch/x86/faults.hh"
+#include "cpu/thread_context.hh"
 
 namespace X86ISA
 {
+
+class Interrupts
+{
+  public:
+    Interrupts()
+    {
+        clear_all();
+    }
+
+    int InterruptLevel(uint64_t softint)
+    {
+        panic("Interrupts don't work on x86!\n");
+        return 0;
+    }
+
+    void post(int int_num, int index)
+    {
+        panic("Interrupts don't work on x86!\n");
+    }
+
+    void clear(int int_num, int index)
+    {
+        panic("Interrupts don't work on x86!\n");
+    }
+
+    void clear_all()
+    {
+        panic("Interrupts don't work on x86!\n");
+    }
+
+    bool check_interrupts(ThreadContext * tc) const
+    {
+        panic("Interrupts don't work on x86!\n");
+        return false;
+    }
+
+    Fault getInterrupt(ThreadContext * tc)
+    {
+        panic("Interrupts don't work on x86!\n");
+        return NoFault;
+    }
+
+    void updateIntrInfo(ThreadContext * tc)
+    {
+        panic("Interrupts don't work on x86!\n");
+    }
+
+    uint64_t get_vec(int int_num)
+    {
+        panic("Interrupts don't work on x86!\n");
+        return 0;
+    }
+
+    void serialize(std::ostream & os)
+    {
+        panic("Interrupts don't work on x86!\n");
+    }
+
+    void unserialize(Checkpoint * cp, const std::string & section)
+    {
+        panic("Interrupts don't work on x86!\n");
+    }
+};
+
 };
 
 #endif // __ARCH_X86_INTERRUPTS_HH__
diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh
index f3478d7f6..e69813836 100644
--- a/src/arch/x86/isa_traits.hh
+++ b/src/arch/x86/isa_traits.hh
@@ -61,6 +61,7 @@
 #include "arch/x86/intregs.hh"
 #include "arch/x86/types.hh"
 #include "arch/x86/x86_traits.hh"
+#include "sim/host.hh"
 
 class StaticInstPtr;
 
@@ -132,6 +133,8 @@ namespace X86ISA
     const int BranchPredAddrShiftAmt = 0;
 
     StaticInstPtr decodeInst(ExtMachInst);
+
+    const Addr LoadAddrMask = ULL(0xffffffffff);
 };
 
 #endif // __ARCH_X86_ISATRAITS_HH__
diff --git a/src/arch/x86/kernel_stats.hh b/src/arch/x86/kernel_stats.hh
index 8cd80073e..7679cb305 100644
--- a/src/arch/x86/kernel_stats.hh
+++ b/src/arch/x86/kernel_stats.hh
@@ -58,10 +58,33 @@
 #ifndef __ARCH_X86_KERNELSTATS_HH__
 #define __ARCH_X86_KERNELSTATS_HH__
 
-#error X86 is not yet supported!
+#include "kern/kernel_stats.hh"
 
-namespace X86ISA
+namespace X86ISA {
+namespace Kernel {
+
+enum cpu_mode {
+    ring0,
+    ring1,
+    ring2,
+    ring3,
+    kernel = ring0,
+    user = ring3,
+    idle,
+    //What is this next one for?
+    cpu_mode_num
+};
+
+extern const char *modestr[];
+
+class Statistics : public ::Kernel::Statistics
 {
+  public:
+    Statistics(System * system) : ::Kernel::Statistics(system)
+    {}
 };
 
+}
+}
+
 #endif // __ARCH_X86_KERNELSTATS_HH__
diff --git a/src/arch/x86/miscregs.hh b/src/arch/x86/miscregs.hh
index bab813719..8080bd90b 100644
--- a/src/arch/x86/miscregs.hh
+++ b/src/arch/x86/miscregs.hh
@@ -61,6 +61,12 @@
 #include "arch/x86/x86_traits.hh"
 #include "base/bitunion.hh"
 
+//These get defined in some system headers (at least termbits.h). That confuses
+//things here significantly.
+#undef CR0
+#undef CR2
+#undef CR3
+
 namespace X86ISA
 {
     enum CondFlagBit {
diff --git a/src/arch/x86/mmaped_ipr.hh b/src/arch/x86/mmaped_ipr.hh
index a33a3f4f0..1fef72fa6 100644
--- a/src/arch/x86/mmaped_ipr.hh
+++ b/src/arch/x86/mmaped_ipr.hh
@@ -75,6 +75,8 @@ namespace X86ISA
     {
 #if !FULL_SYSTEM
         panic("Shouldn't have a memory mapped register in SE\n");
+#else
+        panic("Memory mapped registers aren't implemented for x86!\n");
 #endif
     }
 
@@ -83,6 +85,8 @@ namespace X86ISA
     {
 #if !FULL_SYSTEM
         panic("Shouldn't have a memory mapped register in SE\n");
+#else
+        panic("Memory mapped registers aren't implemented for x86!\n");
 #endif
     }
 };
diff --git a/src/arch/x86/stacktrace.cc b/src/arch/x86/stacktrace.cc
new file mode 100644
index 000000000..bf7059dea
--- /dev/null
+++ b/src/arch/x86/stacktrace.cc
@@ -0,0 +1,227 @@
+/*
+ * Copyright (c) 2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ */
+
+#include <string>
+
+#include "arch/x86/isa_traits.hh"
+#include "arch/x86/stacktrace.hh"
+#include "arch/x86/vtophys.hh"
+#include "base/bitfield.hh"
+#include "base/trace.hh"
+#include "cpu/base.hh"
+#include "cpu/thread_context.hh"
+#include "sim/system.hh"
+
+using namespace std;
+namespace X86ISA
+{
+    ProcessInfo::ProcessInfo(ThreadContext *_tc)
+        : tc(_tc)
+    {
+        Addr addr = 0;
+
+        VirtualPort *vp;
+
+        vp = tc->getVirtPort();
+
+        if (!tc->getSystemPtr()->kernelSymtab->findAddress("thread_info_size", addr))
+            panic("thread info not compiled into kernel\n");
+        thread_info_size = vp->readGtoH<int32_t>(addr);
+
+        if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_size", addr))
+            panic("thread info not compiled into kernel\n");
+        task_struct_size = vp->readGtoH<int32_t>(addr);
+
+        if (!tc->getSystemPtr()->kernelSymtab->findAddress("thread_info_task", addr))
+            panic("thread info not compiled into kernel\n");
+        task_off = vp->readGtoH<int32_t>(addr);
+
+        if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_pid", addr))
+            panic("thread info not compiled into kernel\n");
+        pid_off = vp->readGtoH<int32_t>(addr);
+
+        if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_comm", addr))
+            panic("thread info not compiled into kernel\n");
+        name_off = vp->readGtoH<int32_t>(addr);
+
+        tc->delVirtPort(vp);
+    }
+
+    Addr
+    ProcessInfo::task(Addr ksp) const
+    {
+        Addr base = ksp & ~0x3fff;
+        if (base == ULL(0xfffffc0000000000))
+            return 0;
+
+        Addr tsk;
+
+        VirtualPort *vp;
+
+        vp = tc->getVirtPort();
+        tsk = vp->readGtoH<Addr>(base + task_off);
+        tc->delVirtPort(vp);
+
+        return tsk;
+    }
+
+    int
+    ProcessInfo::pid(Addr ksp) const
+    {
+        Addr task = this->task(ksp);
+        if (!task)
+            return -1;
+
+        uint16_t pd;
+
+        VirtualPort *vp;
+
+        vp = tc->getVirtPort();
+        pd = vp->readGtoH<uint16_t>(task + pid_off);
+        tc->delVirtPort(vp);
+
+        return pd;
+    }
+
+    string
+    ProcessInfo::name(Addr ksp) const
+    {
+        Addr task = this->task(ksp);
+        if (!task)
+            return "console";
+
+        char comm[256];
+        CopyStringOut(tc, comm, task + name_off, sizeof(comm));
+        if (!comm[0])
+            return "startup";
+
+        return comm;
+    }
+
+    StackTrace::StackTrace()
+        : tc(0), stack(64)
+    {
+    }
+
+    StackTrace::StackTrace(ThreadContext *_tc, StaticInstPtr inst)
+        : tc(0), stack(64)
+    {
+        trace(_tc, inst);
+    }
+
+    StackTrace::~StackTrace()
+    {
+    }
+
+    void
+    StackTrace::trace(ThreadContext *_tc, bool is_call)
+    {
+    }
+
+    bool
+    StackTrace::isEntry(Addr addr)
+    {
+        return false;
+    }
+
+    bool
+    StackTrace::decodeStack(MachInst inst, int &disp)
+    {
+        return true;
+    }
+
+    bool
+    StackTrace::decodeSave(MachInst inst, int &reg, int &disp)
+    {
+        return true;
+    }
+
+    /*
+     * Decode the function prologue for the function we're in, and note
+     * which registers are stored where, and how large the stack frame is.
+     */
+    bool
+    StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func,
+                               int &size, Addr &ra)
+    {
+        size = 0;
+        ra = 0;
+
+        for (Addr pc = func; pc < callpc; pc += sizeof(MachInst)) {
+            MachInst inst;
+            CopyOut(tc, (uint8_t *)&inst, pc, sizeof(MachInst));
+
+            int reg, disp;
+            if (decodeStack(inst, disp)) {
+                if (size) {
+                    // panic("decoding frame size again");
+                    return true;
+                }
+                size += disp;
+            } else if (decodeSave(inst, reg, disp)) {
+                if (!ra && reg == ReturnAddressReg) {
+                    CopyOut(tc, (uint8_t *)&ra, sp + disp, sizeof(Addr));
+                    if (!ra) {
+                        // panic("no return address value pc=%#x\n", pc);
+                        return false;
+                    }
+                }
+            }
+        }
+
+        return true;
+    }
+
+#if TRACING_ON
+    void
+    StackTrace::dump()
+    {
+        StringWrap name(tc->getCpuPtr()->name());
+        SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab;
+
+        DPRINTFN("------ Stack ------\n");
+
+        string symbol;
+        for (int i = 0, size = stack.size(); i < size; ++i) {
+            Addr addr = stack[size - i - 1];
+            if (addr == user)
+                symbol = "user";
+            else if (addr == console)
+                symbol = "console";
+            else if (addr == unknown)
+                symbol = "unknown";
+            else
+                symtab->findSymbol(addr, symbol);
+
+            DPRINTFN("%#x: %s\n", addr, symbol);
+        }
+    }
+#endif
+}
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index d2db8cb0b..ad23cb7e4 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -57,6 +57,83 @@
 
 #include <cstring>
 
+#include "config/full_system.hh"
+
+#if FULL_SYSTEM
+
+#include "arch/x86/tlb.hh"
+#include "base/bitfield.hh"
+#include "base/trace.hh"
+#include "cpu/thread_context.hh"
+#include "cpu/base.hh"
+#include "mem/packet_access.hh"
+#include "mem/request.hh"
+#include "sim/system.hh"
+
+namespace X86ISA {
+
+TLB::TLB(const Params *p) : SimObject(p)
+{
+}
+
+Fault
+ITB::translate(RequestPtr &req, ThreadContext *tc)
+{
+    return NoFault;
+}
+
+
+
+Fault
+DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
+{
+    return NoFault;
+};
+
+#if FULL_SYSTEM
+
+Tick
+DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
+{
+    return tc->getCpuPtr()->cycles(1);
+}
+
+Tick
+DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
+{
+    return tc->getCpuPtr()->cycles(1);
+}
+
+#endif
+
+void
+TLB::serialize(std::ostream &os)
+{
+}
+
+void
+TLB::unserialize(Checkpoint *cp, const std::string &section)
+{
+}
+
+void
+DTB::serialize(std::ostream &os)
+{
+    TLB::serialize(os);
+}
+
+void
+DTB::unserialize(Checkpoint *cp, const std::string &section)
+{
+    TLB::unserialize(cp, section);
+}
+
+/* end namespace X86ISA */ }
+
+#else
+
+#include <cstring>
+
 #include "arch/x86/tlb.hh"
 #include "params/X86DTB.hh"
 #include "params/X86ITB.hh"
@@ -76,6 +153,8 @@ namespace X86ISA {
     }
 };
 
+#endif
+
 X86ISA::ITB *
 X86ITBParams::create()
 {
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index 354443794..386d1635d 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -58,6 +58,80 @@
 #ifndef __ARCH_X86_TLB_HH__
 #define __ARCH_X86_TLB_HH__
 
+#include "config/full_system.hh"
+
+#if FULL_SYSTEM
+
+#include "mem/request.hh"
+#include "params/X86DTB.hh"
+#include "params/X86ITB.hh"
+#include "sim/faults.hh"
+#include "sim/sim_object.hh"
+
+class ThreadContext;
+class Packet;
+
+namespace X86ISA
+{
+    struct TlbEntry
+    {
+        Addr pageStart;
+        TlbEntry() {}
+        TlbEntry(Addr paddr) : pageStart(paddr) {}
+
+        void serialize(std::ostream &os);
+        void unserialize(Checkpoint *cp, const std::string &section);
+    };
+
+class TLB : public SimObject
+{
+  public:
+    typedef X86TLBParams Params;
+    TLB(const Params *p);
+
+    void dumpAll();
+
+    // Checkpointing
+    virtual void serialize(std::ostream &os);
+    virtual void unserialize(Checkpoint *cp, const std::string &section);
+};
+
+class ITB : public TLB
+{
+  public:
+    typedef X86ITBParams Params;
+    ITB(const Params *p) : TLB(p)
+    {
+    }
+
+    Fault translate(RequestPtr &req, ThreadContext *tc);
+
+    friend class DTB;
+};
+
+class DTB : public TLB
+{
+  public:
+    typedef X86DTBParams Params;
+    DTB(const Params *p) : TLB(p)
+    {
+    }
+
+    Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
+#if FULL_SYSTEM
+    Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
+    Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
+#endif
+
+    // Checkpointing
+    virtual void serialize(std::ostream &os);
+    virtual void unserialize(Checkpoint *cp, const std::string &section);
+};
+
+}
+
+#else
+
 #include <iostream>
 
 #include "sim/host.hh"
@@ -92,4 +166,6 @@ namespace X86ISA
     };
 };
 
+#endif
+
 #endif // __ARCH_X86_TLB_HH__
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
new file mode 100644
index 000000000..b2532a13e
--- /dev/null
+++ b/src/arch/x86/utility.cc
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use.  Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ *     Director of Intellectual Property Licensing
+ *     Office of Strategy and Technology
+ *     Hewlett-Packard Company
+ *     1501 Page Mill Road
+ *     Palo Alto, California  94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.  Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.  Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.  No right of
+ * sublicense is granted herewith.  Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses.  Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/x86/utility.hh"
+
+namespace X86ISA {
+
+uint64_t getArgument(ThreadContext *tc, int number, bool fp) {
+#if FULL_SYSTEM
+    panic("getArgument() not implemented for x86!\n");
+#else
+    panic("getArgument() only implemented for FULL_SYSTEM\n");
+    M5_DUMMY_RETURN
+#endif
+}
+} //namespace X86_ISA
diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh
index 3f3f1cca3..9497986e6 100644
--- a/src/arch/x86/utility.hh
+++ b/src/arch/x86/utility.hh
@@ -87,6 +87,8 @@ namespace __hash_namespace {
 
 namespace X86ISA
 {
+    uint64_t getArgument(ThreadContext *tc, int number, bool fp);
+
     static inline bool
     inUserMode(ThreadContext *tc)
     {
diff --git a/src/arch/x86/vtophys.cc b/src/arch/x86/vtophys.cc
new file mode 100644
index 000000000..bac2748a4
--- /dev/null
+++ b/src/arch/x86/vtophys.cc
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use.  Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ *     Director of Intellectual Property Licensing
+ *     Office of Strategy and Technology
+ *     Hewlett-Packard Company
+ *     1501 Page Mill Road
+ *     Palo Alto, California  94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.  Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.  Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.  No right of
+ * sublicense is granted herewith.  Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses.  Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include <string>
+
+#include "arch/x86/vtophys.hh"
+
+using namespace std;
+
+namespace X86ISA
+{
+    Addr vtophys(Addr vaddr)
+    {
+        return vaddr;
+    }
+
+    Addr vtophys(ThreadContext *tc, Addr addr)
+    {
+        return addr;
+    }
+}