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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:09 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:09 -0500
commit896c7617c47cd83b0e119b62baa133307d05cecd (patch)
tree9e80ad96c19a94c5194d0661bbc18f8bf52ca5c2 /src/arch
parentaf6b1667e947ec801cbc4568f8ca060ebc976dcd (diff)
downloadgem5-896c7617c47cd83b0e119b62baa133307d05cecd.tar.xz
ARM: Decode the unimplemented data barrier CP15 accesses.
These are CP15DSB (Data Synchronization Barrier), and CP15DMB (Data Memory Barrier).
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/isa/formats/misc.isa6
-rw-r--r--src/arch/arm/miscregs.hh9
2 files changed, 11 insertions, 4 deletions
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index ace90786f..e966fe423 100644
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -104,6 +104,12 @@ def format McrMrc15() {{
case MISCREG_CP15ISB:
return new WarnUnimplemented(
isRead ? "mrc cp15isb" : "mcr cp15isb", machInst);
+ case MISCREG_CP15DSB:
+ return new WarnUnimplemented(
+ isRead ? "mrc cp15dsb" : "mcr cp15dsb", machInst);
+ case MISCREG_CP15DMB:
+ return new WarnUnimplemented(
+ isRead ? "mrc cp15dmb" : "mcr cp15dmb", machInst);
default:
if (isRead) {
return new Mrc15(machInst, rt, (IntRegIndex)miscReg);
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 4d603c65d..fa4c27bd9 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -89,6 +89,8 @@ namespace ArmISA
MISCREG_TPIDRURO,
MISCREG_TPIDRPRW,
MISCREG_CP15ISB,
+ MISCREG_CP15DSB,
+ MISCREG_CP15DMB,
MISCREG_CPACR,
MISCREG_CP15_UNIMP_START,
MISCREG_CTR = MISCREG_CP15_UNIMP_START,
@@ -138,8 +140,6 @@ namespace ArmISA
MISCREG_DCISW,
MISCREG_DCCMVAC,
MISCREG_MCCSW,
- MISCREG_CP15DSB,
- MISCREG_CP15DMB,
MISCREG_DCCMVAU,
MISCREG_CP15_END,
@@ -160,7 +160,8 @@ namespace ArmISA
"fpsr", "fpsid", "fpscr", "fpexc",
"sctlr", "dccisw", "dccimvac",
"contextidr", "tpidrurw", "tpidruro", "tpidrprw",
- "cp15isb", "cpacr", "ctr", "tcmtr", "mpuir", "mpidr", "midr",
+ "cp15isb", "cp15dsb", "cp15dmb", "cpacr",
+ "ctr", "tcmtr", "mpuir", "mpidr", "midr",
"id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
"id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
@@ -169,7 +170,7 @@ namespace ArmISA
"drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
"rgnr", "icialluis", "bpiallis", "iciallu", "icimvau",
"bpiall", "bpimva", "dcimvac", "dcisw", "dccmvac", "mccsw",
- "cp15dsb", "cp15dmb", "dccmvau",
+ "dccmvau",
"nop", "raz"
};