SPARC: Turn on handleIprRead and handleIprWrite in SE in SPARC.

3 files changed, 0 insertions, 14 deletions

diff --git a/src/arch/sparc/mmapped_ipr.hh b/src/arch/sparc/mmapped_ipr.hh
index 28e3ec259..68c73cac0 100644
--- a/src/arch/sparc/mmapped_ipr.hh
+++ b/src/arch/sparc/mmapped_ipr.hh
@@ -48,21 +48,13 @@ namespace SparcISA
 inline Tick
 handleIprRead(ThreadContext *xc, Packet *pkt)
 {
-#if FULL_SYSTEM
     return xc->getDTBPtr()->doMmuRegRead(xc, pkt);
-#else
-    panic("Shouldn't have a memory mapped register in SE\n");
-#endif
 }
 
 inline Tick
 handleIprWrite(ThreadContext *xc, Packet *pkt)
 {
-#if FULL_SYSTEM
     return xc->getDTBPtr()->doMmuRegWrite(xc, pkt);
-#else
-    panic("Shouldn't have a memory mapped register in SE\n");
-#endif
 }
 
 
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index ddc37cf3b..6e390143b 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -840,8 +840,6 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
     translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
 }
 
-#if FULL_SYSTEM
-
 Tick
 TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
 {
@@ -1280,8 +1278,6 @@ doMmuWriteError:
     return tc->getCpuPtr()->ticks(1);
 }
 
-#endif
-
 void
 TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
 {
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index 76ef23b64..7d33f7044 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -167,10 +167,8 @@ class TLB : public BaseTLB
     Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
     void translateTiming(RequestPtr req, ThreadContext *tc,
             Translation *translation, Mode mode);
-#if FULL_SYSTEM
     Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
     Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
-#endif
     void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
 
     // Checkpointing