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authorAli Saidi <saidi@eecs.umich.edu>2006-11-10 20:17:42 -0500
committerAli Saidi <saidi@eecs.umich.edu>2006-11-10 20:17:42 -0500
commitaa19b2e7bca481b5f8fd2c54f2396b53259cf742 (patch)
tree8d628768cc46bbc6e1830e79949768eff06ee22b /src/arch
parent6d54a77518664bc9064211fcf85958b7e2caa9cc (diff)
downloadgem5-aa19b2e7bca481b5f8fd2c54f2396b53259cf742.tar.xz
fix endian issues with condition codes
use memcpy instead of bcopy s/u_int32_t/uint32_t/g fixup endian code to work with solaris hack to make sure htole() works... Nate, have a good idea to fix this? src/arch/sparc/faults.cc: set the reset address to be 40 bits. Makes PC printing easier at least for now. src/arch/sparc/isa/base.isa: fix endian issues with condition codes src/arch/sparc/tlb.hh: add implemented physical addres constants src/arch/sparc/utility.hh: add tlb.hh to utilities src/base/loader/raw_object.cc: add a symbol <filename>_start to the symbol table for binaries files src/base/remote_gdb.cc: use memcpy instead of bcopy src/cpu/exetrace.cc: clean up printing a bit more src/cpu/m5legion_interface.h: add tons to the shared interface src/dev/ethertap.cc: s/u_int32_t/uint32_t/g src/dev/ide_atareg.h: fixup endian code to work with solaris src/dev/pcidev.cc: src/sim/param.hh: hack to make sure htole() works... --HG-- extra : convert_revision : 4579392184b40bcc1062671a953c6595c685e9b2
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/sparc/faults.cc2
-rw-r--r--src/arch/sparc/isa/base.isa7
-rw-r--r--src/arch/sparc/tlb.hh5
-rw-r--r--src/arch/sparc/utility.hh1
4 files changed, 12 insertions, 3 deletions
diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index 2564bc6a9..4cf411d3b 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -494,7 +494,7 @@ void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
void getREDVector(MiscReg TT, Addr & PC, Addr & NPC)
{
//XXX The following constant might belong in a header file.
- const Addr RSTVAddr = 0xFFFFFFFFF0000000ULL;
+ const Addr RSTVAddr = 0xFFF0000000ULL;
PC = RSTVAddr | ((TT << 5) & 0xFF);
NPC = PC + sizeof(MachInst);
}
diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa
index 122ad2b52..aa24c75be 100644
--- a/src/arch/sparc/isa/base.isa
+++ b/src/arch/sparc/isa/base.isa
@@ -244,7 +244,12 @@ output decoder {{
bool passesCondition(uint32_t codes, uint32_t condition)
{
CondCodes condCodes;
- condCodes.bits = codes;
+ condCodes.bits = 0;
+ condCodes.c = codes & 0x1 ? 1 : 0;
+ condCodes.v = codes & 0x2 ? 1 : 0;
+ condCodes.z = codes & 0x4 ? 1 : 0;
+ condCodes.n = codes & 0x8 ? 1 : 0;
+
switch(condition)
{
case Always:
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index 7a9a6aea1..136103f44 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -40,6 +40,9 @@ class ThreadContext;
namespace SparcISA
{
+ const int PAddrImplBits = 40;
+ const Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1;
+
class TLB : public SimObject
{
public:
@@ -59,7 +62,7 @@ namespace SparcISA
{
//For now, always assume the address is already physical.
//Also assume that there are 40 bits of physical address space.
- req->setPaddr(req->getVaddr() & ((1ULL << 40) - 1));
+ req->setPaddr(req->getVaddr() & PAddrImplMask);
return NoFault;
}
};
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index e51677cdf..5c7fe343d 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -33,6 +33,7 @@
#include "arch/sparc/faults.hh"
#include "arch/sparc/isa_traits.hh"
+#include "arch/sparc/tlb.hh"
#include "base/misc.hh"
#include "base/bitfield.hh"
#include "cpu/thread_context.hh"