diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-05 03:22:45 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-05 03:22:45 -0400 |
| commit | f349592071bc6909b441f76bff4eccc8471b1be5 (patch) | |
| tree | f7857d16596656478ec621b9a9a2046910106358 /src/arch | |
| parent | a3f23894ebf8dc237094ea47ef483484e8df412f (diff) | |
| download | gem5-f349592071bc6909b441f76bff4eccc8471b1be5.tar.xz | |
arm: Add missing FPEXC.EN check
Add a missing check to ensure that exceptions are generated properly.
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm/isa/insts/neon.isa | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/arch/arm/isa/insts/neon.isa b/src/arch/arm/isa/insts/neon.isa index 2f1e41f3e..1b20c660d 100644 --- a/src/arch/arm/isa/insts/neon.isa +++ b/src/arch/arm/isa/insts/neon.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2010-2011 ARM Limited +// Copyright (c) 2010-2011, 2015 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -3694,7 +3694,7 @@ let {{ def vdupGprInst(name, Name, opClass, types, rCount): global header_output, exec_output - eWalkCode = ''' + eWalkCode = simdEnabledCheckCode + ''' RegVect destReg; for (unsigned i = 0; i < eCount; i++) { destReg.elements[i] = htog((Element)Op1); @@ -3777,11 +3777,11 @@ let {{ def buildVext(name, Name, opClass, types, rCount, op): global header_output, exec_output - eWalkCode = ''' + eWalkCode = simdEnabledCheckCode + ''' RegVect srcReg1, srcReg2, destReg; ''' for reg in range(rCount): - eWalkCode += simdEnabledCheckCode + ''' + eWalkCode += ''' srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw); srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d_uw); ''' % { "reg" : reg } @@ -3825,7 +3825,7 @@ let {{ def buildVtbxl(name, Name, opClass, length, isVtbl): global header_output, decoder_output, exec_output - code = ''' + code = simdEnabledCheckCode + ''' union { uint8_t bytes[32]; |