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authorAndreas Sandberg <Andreas.Sandberg@arm.com>2013-01-07 13:05:35 -0500
committerAndreas Sandberg <Andreas.Sandberg@arm.com>2013-01-07 13:05:35 -0500
commit0d1ad50326a13a24daed916a069fc9f45775f51d (patch)
tree69402307a753e23fb617538b93ad485f8e5b9598 /src/arch
parent3db3f83a5ea4b9565db1ab6b22d18e2b33ecef98 (diff)
downloadgem5-0d1ad50326a13a24daed916a069fc9f45775f51d.tar.xz
arm: Make ID registers ISA parameters
This patch makes the values of ID_ISARx, MIDR, and FPSID configurable as ISA parameter values. Additionally, setMiscReg now ignores writes to all of the ID registers. Note: This moves the MIDR parameter from ArmSystem to ArmISA for consistency.
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/ArmISA.py40
-rw-r--r--src/arch/arm/ArmSystem.py6
-rw-r--r--src/arch/arm/isa.cc71
-rw-r--r--src/arch/arm/system.cc5
4 files changed, 82 insertions, 40 deletions
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index fc291cfc1..55a589c32 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -35,9 +35,49 @@
#
# Authors: Andreas Sandberg
+from m5.params import *
from m5.SimObject import SimObject
class ArmISA(SimObject):
type = 'ArmISA'
cxx_class = 'ArmISA::ISA'
cxx_header = "arch/arm/isa.hh"
+
+ # 0x35 Implementor is '5' from "M5"
+ # 0x0 Variant
+ # 0xf Architecture from CPUID scheme
+ # 0xc00 Primary part number ("c" or higher implies ARM v7)
+ # 0x0 Revision
+ midr = Param.UInt32(0x350fc000, "Main ID Register")
+
+ # See section B4.1.93 - B4.1.94 of the ARM ARM
+ #
+ # !ThumbEE | !Jazelle | Thumb | ARM
+ # Note: ThumbEE is disabled for now since we don't support CP14
+ # config registers and jumping to ThumbEE vectors
+ id_pfr0 = Param.UInt32(0x00000031, "Processor Feature Register 0")
+ # !Timer | !Virti | !M Profile | !TrustZone | ARMv4
+ id_pfr1 = Param.UInt32(0x00000001, "Processor Feature Register 1")
+
+ # See section B4.1.89 - B4.1.92 of the ARM ARM
+ # VMSAv7 support
+ id_mmfr0 = Param.UInt32(0x00000003, "Memory Model Feature Register 0")
+ id_mmfr1 = Param.UInt32(0x00000000, "Memory Model Feature Register 1")
+ # no HW access | WFI stalling | ISB and DSB |
+ # all TLB maintenance | no Harvard
+ id_mmfr2 = Param.UInt32(0x01230000, "Memory Model Feature Register 2")
+ # SuperSec | Coherent TLB | Bcast Maint |
+ # BP Maint | Cache Maint Set/way | Cache Maint MVA
+ id_mmfr3 = Param.UInt32(0xF0102211, "Memory Model Feature Register 3")
+
+ # See section B4.1.84 of ARM ARM
+ # All values are latest for ARMv7-A profile
+ id_isar0 = Param.UInt32(0x02101111, "Instruction Set Attribute Register 0")
+ id_isar1 = Param.UInt32(0x02112111, "Instruction Set Attribute Register 1")
+ id_isar2 = Param.UInt32(0x21232141, "Instruction Set Attribute Register 2")
+ id_isar3 = Param.UInt32(0x01112131, "Instruction Set Attribute Register 3")
+ id_isar4 = Param.UInt32(0x10010142, "Instruction Set Attribute Register 4")
+ id_isar5 = Param.UInt32(0x00000000, "Instruction Set Attribute Register 5")
+
+
+ fpsid = Param.UInt32(0x410430A0, "Floating-point System ID Register")
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index ce363865c..763b043dc 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -50,12 +50,6 @@ class ArmSystem(System):
type = 'ArmSystem'
cxx_header = "arch/arm/system.hh"
load_addr_mask = 0xffffffff
- # 0x35 Implementor is '5' from "M5"
- # 0x0 Variant
- # 0xf Architecture from CPUID scheme
- # 0xc00 Primary part number ("c" or higher implies ARM v7)
- # 0x0 Revision
- midr_regval = Param.UInt32(0x350fc000, "MIDR value")
multi_proc = Param.Bool(True, "Multiprocessor system?")
boot_loader = Param.String("", "File that contains the boot loader code if any")
gic_cpu_addr = Param.Addr(0, "Addres of the GIC CPU interface")
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 24baa4b0e..99acbb4fd 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -69,8 +69,9 @@ ISA::params() const
void
ISA::clear()
{
+ const Params *p(params());
+
SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
- uint32_t midr = miscRegs[MISCREG_MIDR];
memset(miscRegs, 0, sizeof(miscRegs));
CPSR cpsr = 0;
cpsr.mode = MODE_USER;
@@ -89,9 +90,6 @@ ISA::clear()
miscRegs[MISCREG_SCTLR] = sctlr;
miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
- // Preserve MIDR across reset
- miscRegs[MISCREG_MIDR] = midr;
-
/* Start with an event in the mailbox */
miscRegs[MISCREG_SEV_MAILBOX] = 1;
@@ -152,16 +150,28 @@ ISA::clear()
0; // 1:0
miscRegs[MISCREG_CPACR] = 0;
- miscRegs[MISCREG_FPSID] = 0x410430A0;
- // See section B4.1.84 of ARM ARM
- // All values are latest for ARMv7-A profile
- miscRegs[MISCREG_ID_ISAR0] = 0x02101111;
- miscRegs[MISCREG_ID_ISAR1] = 0x02112111;
- miscRegs[MISCREG_ID_ISAR2] = 0x21232141;
- miscRegs[MISCREG_ID_ISAR3] = 0x01112131;
- miscRegs[MISCREG_ID_ISAR4] = 0x10010142;
- miscRegs[MISCREG_ID_ISAR5] = 0x00000000;
+ // Initialize configurable default values
+ miscRegs[MISCREG_MIDR] = p->midr;
+
+ miscRegs[MISCREG_ID_PFR0] = p->id_pfr0;
+ miscRegs[MISCREG_ID_PFR1] = p->id_pfr1;
+
+ miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
+ miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
+ miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
+ miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
+
+ miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
+ miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
+ miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
+ miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
+ miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
+ miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
+
+
+ miscRegs[MISCREG_FPSID] = p->fpsid;
+
//XXX We need to initialize the rest of the state.
}
@@ -214,14 +224,6 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
tc->cpuId();
}
break;
- case MISCREG_ID_MMFR0:
- return 0x03; // VMSAv7 support
- case MISCREG_ID_MMFR2:
- return 0x01230000; // no HW access | WFI stalling | ISB and DSB
- // | all TLB maintenance | no Harvard
- case MISCREG_ID_MMFR3:
- return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint |
- // BP Maint | Cache Maint Set/way | Cache Maint MVA
case MISCREG_CLIDR:
warn_once("The clidr register always reports 0 caches.\n");
warn_once("clidr LoUIS field of 0b001 to match current "
@@ -231,12 +233,6 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
warn_once("The ccsidr register isn't implemented and "
"always reads as 0.\n");
break;
- case MISCREG_ID_PFR0:
- warn("Returning thumbEE disabled for now since we don't support CP14"
- "config registers and jumping to ThumbEE vectors\n");
- return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM
- case MISCREG_ID_PFR1:
- return 0x00001; // !Timer | !Virti | !M Profile | !TrustZone | ARMv4
case MISCREG_CTR:
{
//all caches have the same line size in gem5
@@ -463,12 +459,29 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
}
return;
}
+
+ case MISCREG_MIDR:
+ case MISCREG_ID_PFR0:
+ case MISCREG_ID_PFR1:
+ case MISCREG_ID_MMFR0:
+ case MISCREG_ID_MMFR1:
+ case MISCREG_ID_MMFR2:
+ case MISCREG_ID_MMFR3:
+ case MISCREG_ID_ISAR0:
+ case MISCREG_ID_ISAR1:
+ case MISCREG_ID_ISAR2:
+ case MISCREG_ID_ISAR3:
+ case MISCREG_ID_ISAR4:
+ case MISCREG_ID_ISAR5:
+
+ case MISCREG_MPIDR:
+ case MISCREG_FPSID:
case MISCREG_TLBTR:
case MISCREG_MVFR0:
case MISCREG_MVFR1:
- case MISCREG_MPIDR:
- case MISCREG_FPSID:
+ // ID registers are constants.
return;
+
case MISCREG_TLBIALLIS:
case MISCREG_TLBIALL:
sys = tc->getSystemPtr();
diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index 380676bbb..b09784b64 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -105,11 +105,6 @@ ArmSystem::initState()
// Set the initial PC to be at start of the kernel code
threadContexts[0]->pcState(kernelEntry & loadAddrMask);
}
-
- for (int i = 0; i < threadContexts.size(); i++) {
- threadContexts[i]->setMiscReg(ArmISA::MISCREG_MIDR,
- p->midr_regval);
- }
}
ArmSystem::~ArmSystem()