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authorGabe Black <gblack@eecs.umich.edu>2007-12-02 00:02:51 -0800
committerGabe Black <gblack@eecs.umich.edu>2007-12-02 00:02:51 -0800
commit5de71e39d87179102c1b6fbde5df1b703188bcf1 (patch)
tree191551a99b174befbe9a1cdd8f81a8b792fb9869 /src/arch
parent4c37f828f1486fe4942c75affee57d8056a17234 (diff)
downloadgem5-5de71e39d87179102c1b6fbde5df1b703188bcf1.tar.xz
X86: Make the 0xA0-0xA3 versions of mov use the right sized immediates.
--HG-- extra : convert_revision : a702403de29772618abb5bd5c5555279d91bdd59
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/x86/isa/insts/general_purpose/data_transfer/move.py4
-rw-r--r--src/arch/x86/predecoder.cc5
2 files changed, 6 insertions, 3 deletions
diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
index 069d1010e..3b8608c48 100644
--- a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
+++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
@@ -60,12 +60,12 @@ microcode = '''
#
def macroop MOV_R_MI {
- limm t1, imm
+ limm t1, imm, dataSize=asz
ld reg, seg, [1, t0, t1]
};
def macroop MOV_MI_R {
- limm t1, imm
+ limm t1, imm, dataSize=asz
st reg, seg, [1, t0, t1]
};
diff --git a/src/arch/x86/predecoder.cc b/src/arch/x86/predecoder.cc
index ace4a6b94..407a09ec0 100644
--- a/src/arch/x86/predecoder.cc
+++ b/src/arch/x86/predecoder.cc
@@ -270,7 +270,10 @@ namespace X86ISA
//Figure out how big of an immediate we'll retreive based
//on the opcode.
int immType = ImmediateType[emi.opcode.num - 1][nextByte];
- immediateSize = SizeTypeToSize[logOpSize - 1][immType];
+ if (emi.opcode.num == 1 && nextByte >= 0xA0 && nextByte <= 0xA3)
+ immediateSize = SizeTypeToSize[logAddrSize - 1][immType];
+ else
+ immediateSize = SizeTypeToSize[logOpSize - 1][immType];
//Determine what to expect next
if (UsesModRM[emi.opcode.num - 1][nextByte]) {