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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-02-25 10:19:47 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-02-25 10:19:47 -0800 |
| commit | cb4141f6e679db9725ad152df89941998535ad95 (patch) | |
| tree | b2b16e7eaff073fa7e1c22ad5c6c6e2f2da9dae1 /src/arch | |
| parent | d48214a6560049643f39873a533f27d5c8895a4e (diff) | |
| download | gem5-cb4141f6e679db9725ad152df89941998535ad95.tar.xz | |
X86: Check src1 for illegal values since that's the index we actually use.
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/x86/isa/microops/regop.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index 4434f9e74..74c93a20a 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -928,7 +928,7 @@ let {{ super(Rdcr, self).__init__(dest, \ src1, "NUM_INTREGS", flags, dataSize) code = ''' - if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) { + if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) { fault = new InvalidOpcode(); } else { DestReg = ControlSrc1; |