SE/FS: Build the Interrupt objects in SE mode.

11 files changed, 195 insertions, 14 deletions

diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript
index e3701d2a4..da27a136e 100644
--- a/src/arch/alpha/SConscript
+++ b/src/arch/alpha/SConscript
@@ -34,6 +34,7 @@ Import('*')
 if env['TARGET_ISA'] == 'alpha':
     Source('ev5.cc')
     Source('faults.cc')
+    Source('interrupts.cc')
     Source('ipr.cc')
     Source('isa.cc')
     Source('pagetable.cc')
@@ -42,14 +43,13 @@ if env['TARGET_ISA'] == 'alpha':
     Source('tlb.cc')
     Source('utility.cc')
 
+    SimObject('AlphaInterrupts.py')
     SimObject('AlphaTLB.py')
 
     if env['FULL_SYSTEM']:
-        SimObject('AlphaInterrupts.py')
         SimObject('AlphaSystem.py')
 
         Source('idle_event.cc')
-        Source('interrupts.cc')
         Source('kernel_stats.cc')
         Source('osfpal.cc')
         Source('stacktrace.cc')
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index a907e52fb..3dee08fbe 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -54,6 +54,7 @@ if env['TARGET_ISA'] == 'arm':
     Source('insts/pred_inst.cc')
     Source('insts/static_inst.cc')
     Source('insts/vfp.cc')
+    Source('interrupts.cc')
     Source('isa.cc')
     Source('miscregs.cc')
     Source('predecoder.cc')
@@ -62,6 +63,7 @@ if env['TARGET_ISA'] == 'arm':
     Source('utility.cc')
     Source('remote_gdb.cc')
 
+    SimObject('ArmInterrupts.py')
     SimObject('ArmNativeTrace.py')
     SimObject('ArmTLB.py')
 
@@ -70,14 +72,12 @@ if env['TARGET_ISA'] == 'arm':
     DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
     DebugFlag('Predecoder', "Instructions returned by the predecoder")
     if env['FULL_SYSTEM']:
-        Source('interrupts.cc')
         Source('stacktrace.cc')
         Source('system.cc')
         Source('vtophys.cc')
         Source('linux/system.cc')
         Source('table_walker.cc')
         
-        SimObject('ArmInterrupts.py')
         SimObject('ArmSystem.py')
     else:
         Source('process.cc')
diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript
index 9fc2b71ff..c842c5507 100644
--- a/src/arch/mips/SConscript
+++ b/src/arch/mips/SConscript
@@ -34,6 +34,7 @@ Import('*')
 
 if env['TARGET_ISA'] == 'mips':
     Source('faults.cc')
+    Source('interrupts.cc')
     Source('isa.cc')
     Source('tlb.cc')
     Source('pagetable.cc')
@@ -41,19 +42,18 @@ if env['TARGET_ISA'] == 'mips':
     Source('dsp.cc')
     Source('remote_gdb.cc')
 
-    SimObject('MipsTLB.py')
+    SimObject('MipsInterrupts.py')
     DebugFlag('MipsPRA')
+    SimObject('MipsTLB.py')
 
     if env['FULL_SYSTEM']:
         SimObject('MipsSystem.py')
-        SimObject('MipsInterrupts.py')
         Source('idle_event.cc')
         Source('mips_core_specific.cc')
         Source('vtophys.cc')
         Source('system.cc')
         Source('stacktrace.cc')
         Source('linux/system.cc')
-        Source('interrupts.cc')
         Source('bare_iron/system.cc')
     else:
         Source('process.cc')
diff --git a/src/arch/mips/interrupts.cc b/src/arch/mips/interrupts.cc
index 096aa628f..f4221ab2c 100755
--- a/src/arch/mips/interrupts.cc
+++ b/src/arch/mips/interrupts.cc
@@ -36,6 +36,7 @@
 #include "arch/mips/pra_constants.hh"
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
+#include "debug/Interrupt.hh"
 
 namespace MipsISA
 {
diff --git a/src/arch/power/PowerInterrupts.py b/src/arch/power/PowerInterrupts.py
new file mode 100644
index 000000000..82d614077
--- /dev/null
+++ b/src/arch/power/PowerInterrupts.py
@@ -0,0 +1,33 @@
+# Copyright (c) 2011 Google
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+from m5.SimObject import SimObject
+
+class PowerInterrupts(SimObject):
+    type = 'PowerInterrupts'
+    cxx_class = 'PowerISA::Interrupts'
diff --git a/src/arch/power/SConscript b/src/arch/power/SConscript
index f96f12757..dc1f8b491 100644
--- a/src/arch/power/SConscript
+++ b/src/arch/power/SConscript
@@ -40,11 +40,14 @@ if env['TARGET_ISA'] == 'power':
     Source('insts/floating.cc')
     Source('insts/condition.cc')
     Source('insts/static_inst.cc')
+    Source('interrupts.cc')
     Source('pagetable.cc')
     Source('tlb.cc')
     Source('utility.cc')
 
+    SimObject('PowerInterrupts.py')
     SimObject('PowerTLB.py')
+
     DebugFlag('Power')
 
     if not env['FULL_SYSTEM']:
diff --git a/src/arch/power/interrupts.cc b/src/arch/power/interrupts.cc
new file mode 100644
index 000000000..c9ef36824
--- /dev/null
+++ b/src/arch/power/interrupts.cc
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2011 Google
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/power/interrupts.hh"
+
+PowerISA::Interrupts *
+PowerInterruptsParams::create()
+{
+    return new PowerISA::Interrupts(this);
+}
diff --git a/src/arch/power/interrupts.hh b/src/arch/power/interrupts.hh
new file mode 100644
index 000000000..9c11c8e8a
--- /dev/null
+++ b/src/arch/power/interrupts.hh
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2011 Google
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_POWER_INTERRUPT_HH__
+#define __ARCH_POWER_INTERRUPT_HH__
+
+#include "base/misc.hh"
+#include "params/PowerInterrupts.hh"
+#include "sim/sim_object.hh"
+
+class ThreadContext;
+
+namespace PowerISA {
+
+class Interrupts : public SimObject
+{
+  private:
+    BaseCPU * cpu;
+
+  public:
+    typedef PowerInterruptsParams Params;
+
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
+
+    Interrupts(Params * p) : SimObject(p), cpu(NULL)
+    {}
+
+    void
+    setCPU(BaseCPU * _cpu)
+    {
+        cpu = _cpu;
+    }
+
+    void
+    post(int int_num, int index)
+    {
+        panic("Interrupts::post not implemented.\n");
+    }
+
+    void
+    clear(int int_num, int index)
+    {
+        panic("Interrupts::clear not implemented.\n");
+    }
+
+    void
+    clearAll()
+    {
+        panic("Interrupts::clearAll not implemented.\n");
+    }
+
+    bool
+    checkInterrupts(ThreadContext *tc) const
+    {
+        panic("Interrupts::checkInterrupts not implemented.\n");
+    }
+
+    Fault
+    getInterrupt(ThreadContext *tc)
+    {
+        panic("Interrupts::getInterrupt not implemented.\n");
+    }
+
+    void
+    updateIntrInfo(ThreadContext *tc)
+    {
+        panic("Interrupts::updateIntrInfo not implemented.\n");
+    }
+};
+
+} // namespace PowerISA
+
+#endif // __ARCH_POWER_INTERRUPT_HH__
+
diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript
index cc13d56af..db2fb9620 100644
--- a/src/arch/sparc/SConscript
+++ b/src/arch/sparc/SConscript
@@ -34,6 +34,7 @@ Import('*')
 if env['TARGET_ISA'] == 'sparc':
     Source('asi.cc')
     Source('faults.cc')
+    Source('interrupts.cc')
     Source('isa.cc')
     Source('nativetrace.cc')
     Source('pagetable.cc')
@@ -41,17 +42,16 @@ if env['TARGET_ISA'] == 'sparc':
     Source('tlb.cc')
     Source('utility.cc')
 
+    SimObject('SparcInterrupts.py')
     SimObject('SparcNativeTrace.py')
-
     SimObject('SparcTLB.py')
+
     DebugFlag('Sparc', "Generic SPARC ISA stuff")
     DebugFlag('RegisterWindows', "Register window manipulation")
 
     if env['FULL_SYSTEM']:
         SimObject('SparcSystem.py')
-        SimObject('SparcInterrupts.py')
 
-        Source('interrupts.cc')
         Source('system.cc')
         Source('ua2005.cc')
         Source('vtophys.cc')
diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript
index 539c55615..1b443cd83 100644
--- a/src/arch/x86/SConscript
+++ b/src/arch/x86/SConscript
@@ -53,6 +53,7 @@ if env['TARGET_ISA'] == 'x86':
     Source('insts/microop.cc')
     Source('insts/microregop.cc')
     Source('insts/static_inst.cc')
+    Source('interrupts.cc')
     Source('isa.cc')
     Source('nativetrace.cc')
     Source('pagetable.cc')
@@ -63,23 +64,22 @@ if env['TARGET_ISA'] == 'x86':
     Source('types.cc')
     Source('utility.cc')
 
+    SimObject('X86LocalApic.py')
     SimObject('X86NativeTrace.py')
     SimObject('X86TLB.py')
 
     DebugFlag('Faults', "Trace all faults/exceptions/traps")
+    DebugFlag('LocalApic', "Local APIC debugging")
     DebugFlag('Predecoder', "Predecoder debug output")
     DebugFlag('X86', "Generic X86 ISA debugging")
 
     if env['FULL_SYSTEM']:
-        DebugFlag('LocalApic', "Local APIC debugging")
         DebugFlag('PageTableWalker', \
                   "Page table walker state machine debugging")
 
-        SimObject('X86LocalApic.py')
         SimObject('X86System.py')
 
         # Full-system sources
-        Source('interrupts.cc')
         Source('linux/system.cc')
         Source('pagetable_walker.cc')
         Source('system.cc')
diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc
index 81cb306dc..55b5bdca9 100644
--- a/src/arch/x86/interrupts.cc
+++ b/src/arch/x86/interrupts.cc
@@ -273,8 +273,10 @@ X86ISA::Interrupts::requestInterrupt(uint8_t vector,
             pendingUnmaskableInt = pendingStartup = true;
             startupVector = vector;
         }
-    } 
+    }
+#if FULL_SYSTEM //XXX CPU has no wakeup method in SE mode.
     cpu->wakeup();
+#endif
 }