diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-04-24 16:38:46 +0000 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-07-07 10:11:16 +0000 |
| commit | feb91ce576f2da6e1941697100d14bc10ace6a90 (patch) | |
| tree | 6af40ee5970c4234f29c3a69c31fe2fe246d5017 /src/arch | |
| parent | 166da650a3c864b31193ade893ed99e547c67644 (diff) | |
| download | gem5-feb91ce576f2da6e1941697100d14bc10ace6a90.tar.xz | |
kvm, arm: Don't forward IRQ/FIQ when using the kernel's GIC
The BaseArmKvmCPU is responsible for forwarding the IRQ and FIQ
signals from gem5's simulated GIC to KVM. However, these signals
shouldn't be used when the in-kernel GIC emulator is used.
Instead of delivering the interrupts to the guest, we should just
ignore them since any such pending interrupts are likely to be an
artifact of CPU switching or incorrect draining.
Change-Id: I083b72639384272157f92f44a6606bdf0be7413c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3660
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm/kvm/base_cpu.cc | 35 | ||||
| -rw-r--r-- | src/arch/arm/kvm/gic.cc | 4 |
2 files changed, 27 insertions, 12 deletions
diff --git a/src/arch/arm/kvm/base_cpu.cc b/src/arch/arm/kvm/base_cpu.cc index e25112cae..765965092 100644 --- a/src/arch/arm/kvm/base_cpu.cc +++ b/src/arch/arm/kvm/base_cpu.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012, 2015 ARM Limited + * Copyright (c) 2012, 2015, 2017 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -88,20 +88,31 @@ BaseArmKvmCPU::startup() Tick BaseArmKvmCPU::kvmRun(Tick ticks) { - bool simFIQ(interrupts[0]->checkRaw(INT_FIQ)); - bool simIRQ(interrupts[0]->checkRaw(INT_IRQ)); + const bool simFIQ(interrupts[0]->checkRaw(INT_FIQ)); + const bool simIRQ(interrupts[0]->checkRaw(INT_IRQ)); - if (fiqAsserted != simFIQ) { - fiqAsserted = simFIQ; - DPRINTF(KvmInt, "KVM: Update FIQ state: %i\n", simFIQ); - vm.setIRQLine(INTERRUPT_VCPU_FIQ(vcpuID), simFIQ); - } - if (irqAsserted != simIRQ) { - irqAsserted = simIRQ; - DPRINTF(KvmInt, "KVM: Update IRQ state: %i\n", simIRQ); - vm.setIRQLine(INTERRUPT_VCPU_IRQ(vcpuID), simIRQ); + if (!vm.hasKernelIRQChip()) { + if (fiqAsserted != simFIQ) { + DPRINTF(KvmInt, "KVM: Update FIQ state: %i\n", simFIQ); + vm.setIRQLine(INTERRUPT_VCPU_FIQ(vcpuID), simFIQ); + } + if (irqAsserted != simIRQ) { + DPRINTF(KvmInt, "KVM: Update IRQ state: %i\n", simIRQ); + vm.setIRQLine(INTERRUPT_VCPU_IRQ(vcpuID), simIRQ); + } + } else { + warn_if(simFIQ && !fiqAsserted, + "FIQ raised by the simulated interrupt controller " \ + "despite in-kernel GIC emulation. This is probably a bug."); + + warn_if(simIRQ && !irqAsserted, + "IRQ raised by the simulated interrupt controller " \ + "despite in-kernel GIC emulation. This is probably a bug."); } + irqAsserted = simIRQ; + fiqAsserted = simFIQ; + return BaseKvmCPU::kvmRun(ticks); } diff --git a/src/arch/arm/kvm/gic.cc b/src/arch/arm/kvm/gic.cc index 498b79faa..ce3baa558 100644 --- a/src/arch/arm/kvm/gic.cc +++ b/src/arch/arm/kvm/gic.cc @@ -54,6 +54,10 @@ KvmKernelGicV2::KvmKernelGicV2(KvmVM &_vm, Addr cpu_addr, Addr dist_addr, vm(_vm), kdev(vm.createDevice(KVM_DEV_TYPE_ARM_VGIC_V2)) { + // Tell the VM that we will emulate the GIC in the kernel. This + // disables IRQ and FIQ handling in the KVM CPU model. + vm.enableKernelIRQChip(); + kdev.setAttr<uint64_t>( KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V2_ADDR_TYPE_DIST, dist_addr); kdev.setAttr<uint64_t>( |