arch: Make the ISA class inherit from SimObject

The ISA class on stores the contents of ID registers on many
architectures. In order to make reset values of such registers
configurable, we make the class inherit from SimObject, which allows
us to use the normal generated parameter headers.

This patch introduces a Python helper method, BaseCPU.createThreads(),
which creates a set of ISAs for each of the threads in an SMT
system. Although it is currently only needed when creating
multi-threaded CPUs, it should always be called before instantiating
the system as this is an obvious place to configure ID registers
identifying a thread/CPU.

24 files changed, 477 insertions, 39 deletions

diff --git a/src/arch/alpha/AlphaISA.py b/src/arch/alpha/AlphaISA.py
new file mode 100644
index 000000000..64c9e4733
--- /dev/null
+++ b/src/arch/alpha/AlphaISA.py
@@ -0,0 +1,43 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.SimObject import SimObject
+
+class AlphaISA(SimObject):
+    type = 'AlphaISA'
+    cxx_class = 'AlphaISA::ISA'
+    cxx_header = "arch/alpha/isa.hh"
diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript
index 421040bb5..f099c5e25 100644
--- a/src/arch/alpha/SConscript
+++ b/src/arch/alpha/SConscript
@@ -59,6 +59,7 @@ if env['TARGET_ISA'] == 'alpha':
     Source('vtophys.cc')
 
     SimObject('AlphaInterrupts.py')
+    SimObject('AlphaISA.py')
     SimObject('AlphaSystem.py')
     SimObject('AlphaTLB.py')
 
diff --git a/src/arch/alpha/isa.cc b/src/arch/alpha/isa.cc
index 5fd34a492..f5660e4f2 100644
--- a/src/arch/alpha/isa.cc
+++ b/src/arch/alpha/isa.cc
@@ -33,11 +33,25 @@
 #include "arch/alpha/isa.hh"
 #include "base/misc.hh"
 #include "cpu/thread_context.hh"
+#include "params/AlphaISA.hh"
 #include "sim/serialize.hh"
 
 namespace AlphaISA
 {
 
+ISA::ISA(Params *p)
+    : SimObject(p)
+{
+    clear();
+    initializeIprTable();
+}
+
+const AlphaISAParams *
+ISA::params() const
+{
+    return dynamic_cast<const Params *>(_params);
+}
+
 void
 ISA::serialize(EventManager *em, std::ostream &os)
 {
@@ -151,3 +165,9 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
 }
 
 }
+
+AlphaISA::ISA *
+AlphaISAParams::create()
+{
+    return new AlphaISA::ISA(this);
+}
diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh
index f1bfcebec..4e22c7eea 100644
--- a/src/arch/alpha/isa.hh
+++ b/src/arch/alpha/isa.hh
@@ -38,7 +38,9 @@
 #include "arch/alpha/registers.hh"
 #include "arch/alpha/types.hh"
 #include "base/types.hh"
+#include "sim/sim_object.hh"
 
+struct AlphaISAParams;
 class BaseCPU;
 class Checkpoint;
 class EventManager;
@@ -46,10 +48,11 @@ class ThreadContext;
 
 namespace AlphaISA
 {
-    class ISA
+    class ISA : public SimObject
     {
       public:
         typedef uint64_t InternalProcReg;
+        typedef AlphaISAParams Params;
 
       protected:
         uint64_t fpcr;       // floating point condition codes
@@ -101,11 +104,9 @@ namespace AlphaISA
             return reg;
         }
 
-        ISA()
-        {
-            clear();
-            initializeIprTable();
-        }
+        const Params *params() const;
+
+        ISA(Params *p);
     };
 }
 
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
new file mode 100644
index 000000000..fc291cfc1
--- /dev/null
+++ b/src/arch/arm/ArmISA.py
@@ -0,0 +1,43 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.SimObject import SimObject
+
+class ArmISA(SimObject):
+    type = 'ArmISA'
+    cxx_class = 'ArmISA::ISA'
+    cxx_header = "arch/arm/isa.hh"
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index 44b6286a0..8d13a9b2d 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -72,6 +72,7 @@ if env['TARGET_ISA'] == 'arm':
     Source('vtophys.cc')
 
     SimObject('ArmInterrupts.py')
+    SimObject('ArmISA.py')
     SimObject('ArmNativeTrace.py')
     SimObject('ArmSystem.py')
     SimObject('ArmTLB.py')
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index ee2799147..24baa4b0e 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -43,6 +43,7 @@
 #include "cpu/checker/cpu.hh"
 #include "debug/Arm.hh"
 #include "debug/MiscRegs.hh"
+#include "params/ArmISA.hh"
 #include "sim/faults.hh"
 #include "sim/stat_control.hh"
 #include "sim/system.hh"
@@ -50,6 +51,21 @@
 namespace ArmISA
 {
 
+ISA::ISA(Params *p)
+    : SimObject(p)
+{
+    SCTLR sctlr;
+    sctlr = 0;
+    miscRegs[MISCREG_SCTLR_RST] = sctlr;
+    clear();
+}
+
+const ArmISAParams *
+ISA::params() const
+{
+    return dynamic_cast<const Params *>(_params);
+}
+
 void
 ISA::clear()
 {
@@ -641,3 +657,9 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
 }
 
 }
+
+ArmISA::ISA *
+ArmISAParams::create()
+{
+    return new ArmISA::ISA(this);
+}
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 48840bf07..9701ce10e 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -47,14 +47,16 @@
 #include "arch/arm/tlb.hh"
 #include "arch/arm/types.hh"
 #include "debug/Checkpoint.hh"
+#include "sim/sim_object.hh"
 
+struct ArmISAParams;
 class ThreadContext;
 class Checkpoint;
 class EventManager;
 
 namespace ArmISA
 {
-    class ISA
+    class ISA : public SimObject
     {
       protected:
         MiscReg miscRegs[NumMiscRegs];
@@ -192,14 +194,11 @@ namespace ArmISA
             updateRegMap(tmp_cpsr);
         }
 
-        ISA()
-        {
-            SCTLR sctlr;
-            sctlr = 0;
-            miscRegs[MISCREG_SCTLR_RST] = sctlr;
+        typedef ArmISAParams Params;
 
-            clear();
-        }
+        const Params *params() const;
+
+        ISA(Params *p);
     };
 }
 
diff --git a/src/arch/mips/MipsISA.py b/src/arch/mips/MipsISA.py
new file mode 100644
index 000000000..bc969a906
--- /dev/null
+++ b/src/arch/mips/MipsISA.py
@@ -0,0 +1,47 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.SimObject import SimObject
+from m5.params import *
+
+class MipsISA(SimObject):
+    type = 'MipsISA'
+    cxx_class = 'MipsISA::ISA'
+    cxx_header = "arch/mips/isa.hh"
+
+    num_threads = Param.UInt8(1, "Maximum number this ISA can handle")
+    num_vpes = Param.UInt8(1, "Maximum number of vpes this ISA can handle")
diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript
index 15b4ffc51..944fc8e55 100644
--- a/src/arch/mips/SConscript
+++ b/src/arch/mips/SConscript
@@ -53,6 +53,7 @@ if env['TARGET_ISA'] == 'mips':
     Source('vtophys.cc')
 
     SimObject('MipsInterrupts.py')
+    SimObject('MipsISA.py')
     SimObject('MipsSystem.py')
     SimObject('MipsTLB.py')
 
diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index f6de102cd..891ed5e2f 100644
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -36,6 +36,7 @@
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "debug/MipsPRA.hh"
+#include "params/MipsISA.hh"
 
 namespace MipsISA
 {
@@ -87,11 +88,10 @@ ISA::miscRegNames[NumMiscRegs] =
     "LLFlag"
 };
 
-ISA::ISA(uint8_t num_threads, uint8_t num_vpes)
+ISA::ISA(Params *p)
+    : SimObject(p),
+      numThreads(p->num_threads), numVpes(p->num_vpes)
 {
-    numThreads = num_threads;
-    numVpes = num_vpes;
-
     miscRegFile.resize(NumMiscRegs);
     bankType.resize(NumMiscRegs);
 
@@ -142,6 +142,12 @@ ISA::ISA(uint8_t num_threads, uint8_t num_vpes)
     clear();
 }
 
+const MipsISAParams *
+ISA::params() const
+{
+    return dynamic_cast<const Params *>(_params);
+}
+
 void
 ISA::clear()
 {
@@ -586,3 +592,9 @@ ISA::CP0Event::unscheduleEvent()
 }
 
 }
+
+MipsISA::ISA *
+MipsISAParams::create()
+{
+    return new MipsISA::ISA(this);
+}
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index a313b4382..3f4477132 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -39,20 +39,24 @@
 #include "arch/mips/types.hh"
 #include "sim/eventq.hh"
 #include "sim/fault_fwd.hh"
+#include "sim/sim_object.hh"
 
 class BaseCPU;
 class Checkpoint;
 class EventManager;
+struct MipsISAParams;
 class ThreadContext;
 
 namespace MipsISA
 {
-    class ISA
+    class ISA : public SimObject
     {
       public:
         // The MIPS name for this file is CP0 or Coprocessor 0
         typedef ISA CP0;
 
+        typedef MipsISAParams Params;
+
       protected:
         // Number of threads and vpes an individual ISA state can handle
         uint8_t numThreads;
@@ -69,8 +73,6 @@ namespace MipsISA
         std::vector<BankType> bankType;
 
       public:
-        ISA(uint8_t num_threads = 1, uint8_t num_vpes = 1);
-
         void clear();
 
         void configCP();
@@ -155,6 +157,9 @@ namespace MipsISA
         static std::string miscRegNames[NumMiscRegs];
 
       public:
+        const Params *params() const;
+
+        ISA(Params *p);
 
         int
         flattenIntIndex(int reg)
diff --git a/src/arch/power/PowerISA.py b/src/arch/power/PowerISA.py
new file mode 100644
index 000000000..df35ab359
--- /dev/null
+++ b/src/arch/power/PowerISA.py
@@ -0,0 +1,43 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.SimObject import SimObject
+
+class PowerISA(SimObject):
+    type = 'PowerISA'
+    cxx_class = 'PowerISA::ISA'
+    cxx_header = "arch/power/isa.hh"
diff --git a/src/arch/power/SConscript b/src/arch/power/SConscript
index a9d20b4bd..f7875cdf5 100644
--- a/src/arch/power/SConscript
+++ b/src/arch/power/SConscript
@@ -44,6 +44,7 @@ if env['TARGET_ISA'] == 'power':
     Source('interrupts.cc')
     Source('linux/linux.cc')
     Source('linux/process.cc')
+    Source('isa.cc')
     Source('pagetable.cc')
     Source('process.cc')
     Source('stacktrace.cc')
@@ -52,6 +53,7 @@ if env['TARGET_ISA'] == 'power':
     Source('vtophys.cc')
 
     SimObject('PowerInterrupts.py')
+    SimObject('PowerISA.py')
     SimObject('PowerTLB.py')
 
     DebugFlag('Power')
diff --git a/src/arch/power/isa.cc b/src/arch/power/isa.cc
new file mode 100644
index 000000000..0b49c9714
--- /dev/null
+++ b/src/arch/power/isa.cc
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Sandberg
+ */
+
+#include "arch/power/isa.hh"
+#include "params/PowerISA.hh"
+
+namespace PowerISA
+{
+
+ISA::ISA(Params *p)
+    : SimObject(p)
+{
+    clear();
+}
+
+const PowerISAParams *
+ISA::params() const
+{
+    return dynamic_cast<const Params *>(_params);
+}
+
+}
+
+PowerISA::ISA *
+PowerISAParams::create()
+{
+    return new PowerISA::ISA(this);
+}
+
diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index 78ae18ea9..446f918f1 100644
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -36,7 +36,9 @@
 #include "arch/power/registers.hh"
 #include "arch/power/types.hh"
 #include "base/misc.hh"
+#include "sim/sim_object.hh"
 
+struct PowerISAParams;
 class ThreadContext;
 class Checkpoint;
 class EventManager;
@@ -44,13 +46,15 @@ class EventManager;
 namespace PowerISA
 {
 
-class ISA
+class ISA : public SimObject
 {
   protected:
     MiscReg dummy;
     MiscReg miscRegs[NumMiscRegs];
 
   public:
+    typedef PowerISAParams Params;
+
     void
     clear()
     {
@@ -104,10 +108,9 @@ class ISA
     {
     }
 
-    ISA()
-    {
-        clear();
-    }
+    const Params *params() const;
+
+    ISA(Params *p);
 };
 
 } // namespace PowerISA
diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript
index 5e2146750..28949aaaf 100644
--- a/src/arch/sparc/SConscript
+++ b/src/arch/sparc/SConscript
@@ -53,6 +53,7 @@ if env['TARGET_ISA'] == 'sparc':
     Source('vtophys.cc')
 
     SimObject('SparcInterrupts.py')
+    SimObject('SparcISA.py')
     SimObject('SparcNativeTrace.py')
     SimObject('SparcSystem.py')
     SimObject('SparcTLB.py')
diff --git a/src/arch/sparc/SparcISA.py b/src/arch/sparc/SparcISA.py
new file mode 100644
index 000000000..23776f673
--- /dev/null
+++ b/src/arch/sparc/SparcISA.py
@@ -0,0 +1,43 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.SimObject import SimObject
+
+class SparcISA(SimObject):
+    type = 'SparcISA'
+    cxx_class = 'SparcISA::ISA'
+    cxx_header = "arch/sparc/isa.hh"
diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc
index b8b4e88cc..0c7e83e8e 100644
--- a/src/arch/sparc/isa.cc
+++ b/src/arch/sparc/isa.cc
@@ -37,6 +37,7 @@
 #include "cpu/thread_context.hh"
 #include "debug/MiscRegs.hh"
 #include "debug/Timer.hh"
+#include "params/SparcISA.hh"
 
 namespace SparcISA
 {
@@ -58,6 +59,22 @@ buildPstateMask()
 
 static const PSTATE PstateMask = buildPstateMask();
 
+ISA::ISA(Params *p)
+    : SimObject(p)
+{
+    tickCompare = NULL;
+    sTickCompare = NULL;
+    hSTickCompare = NULL;
+
+    clear();
+}
+
+const SparcISAParams *
+ISA::params() const
+{
+    return dynamic_cast<const Params *>(_params);
+}
+
 void
 ISA::reloadRegMap()
 {
@@ -780,3 +797,9 @@ ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string &section)
 }
 
 }
+
+SparcISA::ISA *
+SparcISAParams::create()
+{
+    return new SparcISA::ISA(this);
+}
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index 713f01fa5..654cb3507 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -37,14 +37,16 @@
 #include "arch/sparc/registers.hh"
 #include "arch/sparc/types.hh"
 #include "cpu/cpuevent.hh"
+#include "sim/sim_object.hh"
 
 class Checkpoint;
 class EventManager;
+struct SparcISAParams;
 class ThreadContext;
 
 namespace SparcISA
 {
-class ISA
+class ISA : public SimObject
 {
   private:
 
@@ -200,14 +202,10 @@ class ISA
         return reg;
     }
 
-    ISA()
-    {
-        tickCompare = NULL;
-        sTickCompare = NULL;
-        hSTickCompare = NULL;
+    typedef SparcISAParams Params;
+    const Params *params() const;
 
-        clear();
-    }
+    ISA(Params *p);
 };
 }
 
diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript
index 92b30ced1..6ec714e8e 100644
--- a/src/arch/x86/SConscript
+++ b/src/arch/x86/SConscript
@@ -73,6 +73,7 @@ if env['TARGET_ISA'] == 'x86':
     Source('utility.cc')
     Source('vtophys.cc')
 
+    SimObject('X86ISA.py')
     SimObject('X86LocalApic.py')
     SimObject('X86NativeTrace.py')
     SimObject('X86System.py')
diff --git a/src/arch/x86/X86ISA.py b/src/arch/x86/X86ISA.py
new file mode 100644
index 000000000..75d8e85c9
--- /dev/null
+++ b/src/arch/x86/X86ISA.py
@@ -0,0 +1,43 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.SimObject import SimObject
+
+class X86ISA(SimObject):
+    type = 'X86ISA'
+    cxx_class = 'X86ISA::ISA'
+    cxx_header = "arch/x86/isa.hh"
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index 1a9b39840..9dbab8c7e 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -33,6 +33,7 @@
 #include "arch/x86/tlb.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
+#include "params/X86ISA.hh"
 #include "sim/serialize.hh"
 
 namespace X86ISA
@@ -110,6 +111,18 @@ ISA::clear()
     regVal[MISCREG_DR7] = 1 << 10;
 }
 
+ISA::ISA(Params *p)
+    : SimObject(p)
+{
+    clear();
+}
+
+const X86ISAParams *
+ISA::params() const
+{
+    return dynamic_cast<const Params *>(_params);
+}
+
 MiscReg
 ISA::readMiscRegNoEffect(int miscReg)
 {
@@ -376,3 +389,9 @@ ISA::unserialize(EventManager *em, Checkpoint * cp,
 }
 
 }
+
+X86ISA::ISA *
+X86ISAParams::create()
+{
+    return new X86ISA::ISA(this);
+}
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index 7b0c7b61a..39ed68ea5 100644
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -38,14 +38,16 @@
 #include "arch/x86/regs/misc.hh"
 #include "arch/x86/registers.hh"
 #include "base/types.hh"
+#include "sim/sim_object.hh"
 
 class Checkpoint;
 class EventManager;
 class ThreadContext;
+struct X86ISAParams;
 
 namespace X86ISA
 {
-    class ISA
+    class ISA : public SimObject
     {
       protected:
         MiscReg regVal[NUM_MISCREGS];
@@ -54,12 +56,12 @@ namespace X86ISA
                 ThreadContext *tc);
 
       public:
+        typedef X86ISAParams Params;
+
         void clear();
 
-        ISA()
-        {
-            clear();
-        }
+        ISA(Params *p);
+        const Params *params() const;
 
         MiscReg readMiscRegNoEffect(int miscReg);
         MiscReg readMiscReg(int miscReg, ThreadContext *tc);