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authorAustin Harris <austinharris@utexas.edu>2018-07-07 15:43:27 -0500
committerAustin Harris <austin.dane.harris@gmail.com>2018-07-09 01:53:49 +0000
commit98cbcbb54f56475759fae747b60e47568617640f (patch)
treeaa8a1e2a566aa1d5086ead641364b2b323371086 /src/arch
parent0ee4a543648a4c183a27b7d953317a99f6f30928 (diff)
downloadgem5-98cbcbb54f56475759fae747b60e47568617640f.tar.xz
arch-riscv: Fix the srlw and srliw instructions.
Change-Id: I14ccb0655819887db2306fee1188e1c83a991743 Signed-off-by: Austin Harris <austinharris@utexas.edu> Reviewed-on: https://gem5-review.googlesource.com/11669 Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com>
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/riscv/isa/decoder.isa4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index d8f3395e3..b4bf3854b 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -447,7 +447,7 @@ decode QUADRANT default Unknown::unknown() {
}});
0x5: decode SRTYPE {
0x0: srliw({{
- Rd = Rs1_uw >> SHAMT5;
+ Rd_sd = (int32_t)(Rs1_uw >> SHAMT5);
}});
0x1: sraiw({{
Rd_sd = Rs1_sw >> SHAMT5;
@@ -759,7 +759,7 @@ decode QUADRANT default Unknown::unknown() {
}}, IntDivOp);
0x5: decode FUNCT7 {
0x0: srlw({{
- Rd_uw = Rs1_uw >> Rs2<4:0>;
+ Rd_sd = (int32_t)(Rs1_uw >> Rs2<4:0>);
}});
0x1: divuw({{
if (Rs2_uw == 0) {