merge

20 files changed, 212 insertions, 148 deletions

diff --git a/src/arch/arm/linux/linux.hh b/src/arch/arm/linux/linux.hh
index e0545761d..16bcee47a 100644
--- a/src/arch/arm/linux/linux.hh
+++ b/src/arch/arm/linux/linux.hh
@@ -47,22 +47,22 @@ class ArmLinux : public Linux
 
     //@{
     /// open(2) flag values.
-    static const int TGT_O_RDONLY	= 0x00000000;	//!< O_RDONLY
-    static const int TGT_O_WRONLY	= 0x00000001;	//!< O_WRONLY
-    static const int TGT_O_RDWR	        = 0x00000002;	//!< O_RDWR
-    static const int TGT_O_CREAT	= 0x00000100;	//!< O_CREAT
-    static const int TGT_O_EXCL	        = 0x00000200;	//!< O_EXCL
-    static const int TGT_O_NOCTTY	= 0x00000400;	//!< O_NOCTTY
-    static const int TGT_O_TRUNC	= 0x00001000;	//!< O_TRUNC
-    static const int TGT_O_APPEND	= 0x00002000;	//!< O_APPEND
-    static const int TGT_O_NONBLOCK     = 0x00004000;	//!< O_NONBLOCK
-    static const int TGT_O_SYNC	        = 0x00010000;	//!< O_SYNC
-    static const int TGT_FASYNC		= 0x00020000;	//!< FASYNC
-    static const int TGT_O_DIRECT	= 0x00040000;	//!< O_DIRECT
-    static const int TGT_O_LARGEFILE	= 0x00100000;	//!< O_LARGEFILE
-    static const int TGT_O_DIRECTORY	= 0x00200000;	//!< O_DIRECTORY
-    static const int TGT_O_NOFOLLOW	= 0x00400000;	//!< O_NOFOLLOW
-    static const int TGT_O_NOATIME	= 0x01000000;	//!< O_NOATIME
+    static const int TGT_O_RDONLY    = 00000000; //!< O_RDONLY
+    static const int TGT_O_WRONLY    = 00000001; //!< O_WRONLY
+    static const int TGT_O_RDWR      = 00000002; //!< O_RDWR
+    static const int TGT_O_CREAT     = 00000100; //!< O_CREAT
+    static const int TGT_O_EXCL      = 00000200; //!< O_EXCL
+    static const int TGT_O_NOCTTY    = 00000400; //!< O_NOCTTY
+    static const int TGT_O_TRUNC     = 00001000; //!< O_TRUNC
+    static const int TGT_O_APPEND    = 00002000; //!< O_APPEND
+    static const int TGT_O_NONBLOCK  = 00004000; //!< O_NONBLOCK
+    static const int TGT_O_SYNC      = 00010000; //!< O_SYNC
+    static const int TGT_FASYNC      = 00020000; //!< FASYNC
+    static const int TGT_O_DIRECTORY = 00040000; //!< O_DIRECTORY
+    static const int TGT_O_NOFOLLOW  = 00100000; //!< O_NOFOLLOW
+    static const int TGT_O_DIRECT    = 00200000; //!< O_DIRECT
+    static const int TGT_O_LARGEFILE = 00400000; //!< O_LARGEFILE
+    static const int TGT_O_NOATIME   = 01000000; //!< O_NOATIME
     //@}
 
     /// For mmap().
@@ -70,13 +70,13 @@ class ArmLinux : public Linux
 
     //@{
     /// For getsysinfo().
-    static const unsigned GSI_PLATFORM_NAME = 103;  //!< platform name as string
-    static const unsigned GSI_CPU_INFO = 59;	//!< CPU information
-    static const unsigned GSI_PROC_TYPE = 60;	//!< get proc_type
-    static const unsigned GSI_MAX_CPU = 30;         //!< max # cpu's on this machine
-    static const unsigned GSI_CPUS_IN_BOX = 55;	//!< number of CPUs in system
-    static const unsigned GSI_PHYSMEM = 19;	        //!< Physical memory in KB
-    static const unsigned GSI_CLK_TCK = 42;	        //!< clock freq in Hz
+    static const unsigned GSI_PLATFORM_NAME = 103; //!< platform name as string
+    static const unsigned GSI_CPU_INFO = 59;       //!< CPU information
+    static const unsigned GSI_PROC_TYPE = 60;      //!< get proc_type
+    static const unsigned GSI_MAX_CPU = 30;        //!< max # cpu's on this machine
+    static const unsigned GSI_CPUS_IN_BOX = 55;    //!< number of CPUs in system
+    static const unsigned GSI_PHYSMEM = 19;        //!< Physical memory in KB
+    static const unsigned GSI_CLK_TCK = 42;        //!< clock freq in Hz
     //@}
 
     //@{
diff --git a/src/arch/x86/floatregs.hh b/src/arch/x86/floatregs.hh
index dc9867c42..2108db8d5 100644
--- a/src/arch/x86/floatregs.hh
+++ b/src/arch/x86/floatregs.hh
@@ -166,7 +166,7 @@ namespace X86ISA
     static inline FloatRegIndex
     FLOATREG_STACK(int index, int top)
     {
-        return (FloatRegIndex)(NUM_FLOATREGS + ((top + index + 8) % 8));
+        return FLOATREG_FPR((top + index + 8) % 8);
     }
 };
 
diff --git a/src/arch/x86/insts/microfpop.hh b/src/arch/x86/insts/microfpop.hh
index 2e01cadbc..d3cecd67b 100644
--- a/src/arch/x86/insts/microfpop.hh
+++ b/src/arch/x86/insts/microfpop.hh
@@ -80,13 +80,13 @@ namespace X86ISA
                 const char *mnem, const char *_instMnem,
                 bool isMicro, bool isDelayed,
                 bool isFirst, bool isLast,
-                RegIndex _src1, RegIndex _src2, RegIndex _dest,
+                InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
                 uint8_t _dataSize, int8_t _spm,
                 OpClass __opClass) :
             X86MicroopBase(_machInst, mnem, _instMnem,
                     isMicro, isDelayed, isFirst, isLast,
                     __opClass),
-            src1(_src1), src2(_src2), dest(_dest),
+            src1(_src1.idx), src2(_src2.idx), dest(_dest.idx),
             dataSize(_dataSize), spm(_spm)
         {}
 /*
diff --git a/src/arch/x86/insts/microldstop.hh b/src/arch/x86/insts/microldstop.hh
index ec9cb52b3..309a2e6b7 100644
--- a/src/arch/x86/insts/microldstop.hh
+++ b/src/arch/x86/insts/microldstop.hh
@@ -93,20 +93,21 @@ namespace X86ISA
         LdStOp(ExtMachInst _machInst,
                 const char * mnem, const char * _instMnem,
                 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
-                uint8_t _scale, RegIndex _index, RegIndex _base,
-                uint64_t _disp, uint8_t _segment,
-                RegIndex _data,
+                uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
+                uint64_t _disp, InstRegIndex _segment,
+                InstRegIndex _data,
                 uint8_t _dataSize, uint8_t _addressSize,
                 Request::FlagsType _memFlags,
                 OpClass __opClass) :
         X86MicroopBase(machInst, mnem, _instMnem,
                 isMicro, isDelayed, isFirst, isLast, __opClass),
-                scale(_scale), index(_index), base(_base),
-                disp(_disp), segment(_segment),
-                data(_data),
+                scale(_scale), index(_index.idx), base(_base.idx),
+                disp(_disp), segment(_segment.idx),
+                data(_data.idx),
                 dataSize(_dataSize), addressSize(_addressSize),
-                memFlags(_memFlags | _segment)
+                memFlags(_memFlags | _segment.idx)
         {
+            assert(_segment.idx < NUM_SEGMENTREGS);
             foldOBit = (dataSize == 1 && !_machInst.rex.present) ? 1 << 6 : 0;
             foldABit =
                 (addressSize == 1 && !_machInst.rex.present) ? 1 << 6 : 0;
diff --git a/src/arch/x86/insts/microregop.hh b/src/arch/x86/insts/microregop.hh
index d805adb33..16e1afc0a 100644
--- a/src/arch/x86/insts/microregop.hh
+++ b/src/arch/x86/insts/microregop.hh
@@ -79,13 +79,13 @@ namespace X86ISA
                 const char *mnem, const char *_instMnem,
                 bool isMicro, bool isDelayed,
                 bool isFirst, bool isLast,
-                RegIndex _src1, RegIndex _dest,
+                InstRegIndex _src1, InstRegIndex _dest,
                 uint8_t _dataSize, uint16_t _ext,
                 OpClass __opClass) :
             X86MicroopBase(_machInst, mnem, _instMnem,
                     isMicro, isDelayed, isFirst, isLast,
                     __opClass),
-            src1(_src1), dest(_dest),
+            src1(_src1.idx), dest(_dest.idx),
             dataSize(_dataSize), ext(_ext)
         {
             foldOBit = (dataSize == 1 && !_machInst.rex.present) ? 1 << 6 : 0;
@@ -107,14 +107,14 @@ namespace X86ISA
                 const char *mnem, const char *_instMnem,
                 bool isMicro, bool isDelayed,
                 bool isFirst, bool isLast,
-                RegIndex _src1, RegIndex _src2, RegIndex _dest,
+                InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
                 uint8_t _dataSize, uint16_t _ext,
                 OpClass __opClass) :
             RegOpBase(_machInst, mnem, _instMnem,
                     isMicro, isDelayed, isFirst, isLast,
                     _src1, _dest, _dataSize, _ext,
                     __opClass),
-            src2(_src2)
+            src2(_src2.idx)
         {
         }
 
@@ -132,7 +132,7 @@ namespace X86ISA
                 const char * mnem, const char *_instMnem,
                 bool isMicro, bool isDelayed,
                 bool isFirst, bool isLast,
-                RegIndex _src1, uint8_t _imm8, RegIndex _dest,
+                InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest,
                 uint8_t _dataSize, uint16_t _ext,
                 OpClass __opClass) :
             RegOpBase(_machInst, mnem, _instMnem,
diff --git a/src/arch/x86/insts/static_inst.hh b/src/arch/x86/insts/static_inst.hh
index 8480f2713..4ca7a4984 100644
--- a/src/arch/x86/insts/static_inst.hh
+++ b/src/arch/x86/insts/static_inst.hh
@@ -64,6 +64,18 @@
 namespace X86ISA
 {
     /**
+     * Class for register indices passed to instruction constructors. Using a
+     * wrapper struct for these lets take advantage of the compiler's type
+     * checking.
+     */
+    struct InstRegIndex
+    {
+        RegIndex idx;
+        explicit InstRegIndex(RegIndex _idx) : idx(_idx)
+        {}
+    };
+
+    /**
      * Base class for all X86 static instructions.
      */
 
diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa
index 3ac9cd4f9..78046c0c8 100644
--- a/src/arch/x86/isa/includes.isa
+++ b/src/arch/x86/isa/includes.isa
@@ -109,6 +109,8 @@ output header {{
 #include "cpu/static_inst.hh"
 #include "mem/packet.hh"
 #include "sim/faults.hh"
+
+using X86ISA::InstRegIndex;
 }};
 
 output decoder {{
diff --git a/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py b/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py
index 22364e038..da10d8478 100644
--- a/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py
+++ b/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py
@@ -84,7 +84,7 @@
 microcode = '''
 def macroop BSR_R_R {
     # Determine if the input was zero, and also move it to a temp reg.
-    movi t1, t1, t0, dataSize=8
+    mov t1, t1, t0, dataSize=8
     and t1, regm, regm, flags=(ZF,)
     br label("end"), flags=(CZF,)
 
@@ -132,7 +132,7 @@ end:
 
 def macroop BSR_R_M {
 
-    movi t1, t1, t0, dataSize=8
+    mov t1, t1, t0, dataSize=8
     ld t1, seg, sib, disp
 
     # Determine if the input was zero, and also move it to a temp reg.
@@ -184,7 +184,7 @@ end:
 def macroop BSR_R_P {
 
     rdip t7
-    movi t1, t1, t0, dataSize=8
+    mov t1, t1, t0, dataSize=8
     ld t1, seg, riprel, disp
 
     # Determine if the input was zero, and also move it to a temp reg.
diff --git a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
index 358fe43c8..a9ad611b7 100644
--- a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
+++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
@@ -143,7 +143,7 @@ processCSDescriptor:
     # appropriate/other RIP checks.
     # if temp_RIP > CS.limit throw #GP(0)
     rdlimit t6, cs, dataSize=8
-    subi t0, t1, t6, flags=(ECF,)
+    sub t0, t1, t6, flags=(ECF,)
     fault "new GeneralProtection(0)", flags=(CECF,)
 
     #(temp_CPL!=CPL)
diff --git a/src/arch/x86/isa/insts/general_purpose/control_transfer/jump.py b/src/arch/x86/isa/insts/general_purpose/control_transfer/jump.py
index 4f0cdf770..461861b0d 100644
--- a/src/arch/x86/isa/insts/general_purpose/control_transfer/jump.py
+++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/jump.py
@@ -118,7 +118,7 @@ def macroop JMP_FAR_I
     limm t2, imm, dataSize=8
     # Figure out the width of the offset.
     limm t3, dsz, dataSize=8
-    sll t3, t3, 3, dataSize=8
+    slli t3, t3, 3, dataSize=8
     # Get the selector into t1.
     sll t1, t2, t3, dataSize=8
     mov t1, t0, t1, dataSize=2
@@ -178,7 +178,7 @@ def macroop JMP_FAR_REAL_I
     limm t2, imm, dataSize=8
     # Figure out the width of the offset.
     limm t3, dsz, dataSize=8
-    sll t3, t3, 3, dataSize=8
+    slli t3, t3, 3, dataSize=8
     # Get the selector into t1.
     sll t1, t2, t3, dataSize=8
     mov t1, t0, t1, dataSize=2
diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py
index 82fdffc63..f4c8a4663 100644
--- a/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py
+++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py
@@ -163,7 +163,7 @@ def macroop ENTER_I_I {
     # Pull the different components out of the immediate
     limm t1, imm
     zexti t2, t1, 15, dataSize=8
-    srl t1, t1, 16
+    srli t1, t1, 16
     zexti t1, t1, 5, dataSize=8
     # t1 is now the masked nesting level, and t2 is the amount of storage.
 
@@ -174,7 +174,7 @@ def macroop ENTER_I_I {
     mov t6, t6, rsp, dataSize=asz
 
     # If the nesting level is zero, skip all this stuff.
-    subi t0, t1, t0, flags=(EZF,), dataSize=2
+    sub t0, t1, t0, flags=(EZF,), dataSize=2
     br label("skipLoop"), flags=(CEZF,)
 
     # If the level was 1, only push the saved rbp
diff --git a/src/arch/x86/isa/insts/general_purpose/system_calls.py b/src/arch/x86/isa/insts/general_purpose/system_calls.py
index 9501116d9..31184eae7 100644
--- a/src/arch/x86/isa/insts/general_purpose/system_calls.py
+++ b/src/arch/x86/isa/insts/general_purpose/system_calls.py
@@ -65,7 +65,7 @@ def macroop SYSCALL_64
     # Stick rflags with RF masked into r11.
     rflags t2
     limm t3, "~RFBit", dataSize=8
-    andi r11, t2, t3, dataSize=8
+    and r11, t2, t3, dataSize=8
 
     rdval t3, star
     srli t3, t3, 32, dataSize=8
@@ -118,7 +118,7 @@ def macroop SYSCALL_COMPAT
     # Stick rflags with RF masked into r11.
     rflags t2
     limm t3, "~RFBit", dataSize=8
-    andi r11, t2, t3, dataSize=8
+    and r11, t2, t3, dataSize=8
 
     rdval t3, star
     srli t3, t3, 32, dataSize=8
diff --git a/src/arch/x86/isa/insts/system/control_registers.py b/src/arch/x86/isa/insts/system/control_registers.py
index 82811bb07..da105e411 100644
--- a/src/arch/x86/isa/insts/system/control_registers.py
+++ b/src/arch/x86/isa/insts/system/control_registers.py
@@ -28,58 +28,58 @@
 
 microcode = '''
 def macroop CLTS {
-    rdcr t1, 0, dataSize=8
+    rdcr t1, regIdx(0), dataSize=8
     andi t1, t1, 0xF7, dataSize=1
-    wrcr 0, t1, dataSize=8
+    wrcr regIdx(0), t1, dataSize=8
 };
 
 def macroop LMSW_R {
-    rdcr t1, 0, dataSize=8
+    rdcr t1, regIdx(0), dataSize=8
     # This logic sets MP, EM, and TS to whatever is in the operand. It will
     # set PE but not clear it.
     limm t2, "~ULL(0xe)", dataSize=8
     and t1, t1, t2, dataSize=8
     andi t2, reg, 0xf, dataSize=8
     or t1, t1, t2, dataSize=8
-    wrcr 0, t1, dataSize=8
+    wrcr regIdx(0), t1, dataSize=8
 };
 
 def macroop LMSW_M {
     ld t3, seg, sib, disp, dataSize=2
-    rdcr t1, 0, dataSize=8
+    rdcr t1, regIdx(0), dataSize=8
     # This logic sets MP, EM, and TS to whatever is in the operand. It will
     # set PE but not clear it.
     limm t2, "~ULL(0xe)", dataSize=8
     and t1, t1, t2, dataSize=8
     andi t2, t3, 0xf, dataSize=8
     or t1, t1, t2, dataSize=8
-    wrcr 0, t1, dataSize=8
+    wrcr regIdx(0), t1, dataSize=8
 };
 
 def macroop LMSW_P {
     rdip t7, dataSize=asz
     ld t3, seg, riprel, disp, dataSize=2
-    rdcr t1, 0, dataSize=8
+    rdcr t1, regIdx(0), dataSize=8
     # This logic sets MP, EM, and TS to whatever is in the operand. It will
     # set PE but not clear it.
     limm t2, "~ULL(0xe)", dataSize=8
     and t1, t1, t2, dataSize=8
     andi t2, t3, 0xf, dataSize=8
     or t1, t1, t2, dataSize=8
-    wrcr 0, t1, dataSize=8
+    wrcr regIdx(0), t1, dataSize=8
 };
 
 def macroop SMSW_R {
-    rdcr reg, 0
+    rdcr reg, regIdx(0)
 };
 
 def macroop SMSW_M {
-    rdcr t1, 0
+    rdcr t1, regIdx(0)
     st t1, seg, sib, disp, dataSize=2
 };
 
 def macroop SMSW_P {
-    rdcr t1, 0
+    rdcr t1, regIdx(0)
     rdip t7, dataSize=asz
     st t1, seg, riprel, disp, dataSize=2
 };
diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa
index c7c6dae2e..0cc72bf7b 100644
--- a/src/arch/x86/isa/microasm.isa
+++ b/src/arch/x86/isa/microasm.isa
@@ -75,14 +75,22 @@ let {{
     from micro_asm import MicroAssembler, Rom_Macroop
     mainRom = X86MicrocodeRom('main ROM')
     assembler = MicroAssembler(X86Macroop, microopClasses, mainRom, Rom_Macroop)
+
+    def regIdx(idx):
+        return "InstRegIndex(%s)" % idx
+
+    assembler.symbols["regIdx"] = regIdx
+
     # Add in symbols for the microcode registers
     for num in range(16):
-        assembler.symbols["t%d" % num] = "NUM_INTREGS+%d" % num
+        assembler.symbols["t%d" % num] = regIdx("NUM_INTREGS+%d" % num)
     for num in range(8):
-        assembler.symbols["ufp%d" % num] = "FLOATREG_MICROFP(%d)" % num
+        assembler.symbols["ufp%d" % num] = \
+            regIdx("FLOATREG_MICROFP(%d)" % num)
     # Add in symbols for the segment descriptor registers
     for letter in ("C", "D", "E", "F", "G", "H", "S"):
-        assembler.symbols["%ss" % letter.lower()] = "SEGMENT_REG_%sS" % letter
+        assembler.symbols["%ss" % letter.lower()] = \
+            regIdx("SEGMENT_REG_%sS" % letter)
 
     # Add in symbols for the various checks of segment selectors.
     for check in ("NoCheck", "CSCheck", "CallGateCheck", "IntGateCheck",
@@ -91,25 +99,25 @@ let {{
         assembler.symbols[check] = "Seg%s" % check
 
     for reg in ("TR", "IDTR"):
-        assembler.symbols[reg.lower()] = "SYS_SEGMENT_REG_%s" % reg
+        assembler.symbols[reg.lower()] = regIdx("SYS_SEGMENT_REG_%s" % reg)
 
     for reg in ("TSL", "TSG"):
-        assembler.symbols[reg.lower()] = "SEGMENT_REG_%s" % reg
+        assembler.symbols[reg.lower()] = regIdx("SEGMENT_REG_%s" % reg)
 
     # Miscellaneous symbols
     symbols = {
-        "reg" : "env.reg",
-        "xmml" : "FLOATREG_XMM_LOW(env.reg)",
-        "xmmh" : "FLOATREG_XMM_HIGH(env.reg)",
-        "regm" : "env.regm",
-        "xmmlm" : "FLOATREG_XMM_LOW(env.regm)",
-        "xmmhm" : "FLOATREG_XMM_HIGH(env.regm)",
+        "reg" : regIdx("env.reg"),
+        "xmml" : regIdx("FLOATREG_XMM_LOW(env.reg)"),
+        "xmmh" : regIdx("FLOATREG_XMM_HIGH(env.reg)"),
+        "regm" : regIdx("env.regm"),
+        "xmmlm" : regIdx("FLOATREG_XMM_LOW(env.regm)"),
+        "xmmhm" : regIdx("FLOATREG_XMM_HIGH(env.regm)"),
         "imm" : "adjustedImm",
         "disp" : "adjustedDisp",
-        "seg" : "env.seg",
+        "seg" : regIdx("env.seg"),
         "scale" : "env.scale",
-        "index" : "env.index",
-        "base" : "env.base",
+        "index" : regIdx("env.index"),
+        "base" : regIdx("env.base"),
         "dsz" : "env.dataSize",
         "asz" : "env.addressSize",
         "ssz" : "env.stackSize"
@@ -133,17 +141,18 @@ let {{
 
     # This segment selects an internal address space mapped to MSRs,
     # CPUID info, etc.
-    assembler.symbols["intseg"] = "SEGMENT_REG_MS"
+    assembler.symbols["intseg"] = regIdx("SEGMENT_REG_MS")
     # This segment always has base 0, and doesn't imply any special handling
     # like the internal segment above
-    assembler.symbols["flatseg"] = "SEGMENT_REG_LS"
+    assembler.symbols["flatseg"] = regIdx("SEGMENT_REG_LS")
 
     for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di', \
                 '8',  '9',  '10', '11', '12', '13', '14', '15'):
-        assembler.symbols["r%s" % reg] = "INTREG_R%s" % reg.upper()
+        assembler.symbols["r%s" % reg] = \
+            regIdx("INTREG_R%s" % reg.upper())
 
     for reg in range(16):
-        assembler.symbols["cr%d" % reg] = "MISCREG_CR%d" % reg
+        assembler.symbols["cr%d" % reg] = regIdx("MISCREG_CR%d" % reg)
 
     for flag in ('CF', 'PF', 'ECF', 'AF', 'EZF', 'ZF', 'SF', 'OF', \
                  'TF', 'IF', 'NT', 'RF', 'VM', 'AC', 'VIF', 'VIP', 'ID'):
@@ -164,7 +173,7 @@ let {{
     for reg in ('sysenter_cs', 'sysenter_esp', 'sysenter_eip',
                 'star', 'lstar', 'cstar', 'sf_mask',
                 'kernel_gs_base'):
-        assembler.symbols[reg] = "MISCREG_%s" % reg.upper()
+        assembler.symbols[reg] = regIdx("MISCREG_%s" % reg.upper())
 
     # Code literal which forces a default 64 bit operand size in 64 bit mode.
     assembler.symbols["oszIn64Override"] = '''
@@ -201,7 +210,7 @@ let {{
     assembler.symbols["rom_local_label"] = rom_local_labeler
 
     def stack_index(index):
-        return "(NUM_FLOATREGS + (((%s) + 8) %% 8))" % index
+        return regIdx("NUM_FLOATREGS + (((%s) + 8) %% 8)" % index)
 
     assembler.symbols["st"] = stack_index
 
diff --git a/src/arch/x86/isa/microops/base.isa b/src/arch/x86/isa/microops/base.isa
index f1007bf71..8541df831 100644
--- a/src/arch/x86/isa/microops/base.isa
+++ b/src/arch/x86/isa/microops/base.isa
@@ -86,7 +86,7 @@ let {{
                 const EmulEnv &env =
                     macroop ? macroop->getEmulEnv() : dummyEmulEnv;
                 // env may not be used in the microop's constructor.
-                RegIndex reg = env.reg;
+                InstRegIndex reg(env.reg);
                 reg = reg;
                 using namespace RomLabels;
                 return %s;
diff --git a/src/arch/x86/isa/microops/fpop.isa b/src/arch/x86/isa/microops/fpop.isa
index d4acfdbf4..e49bd8a20 100644
--- a/src/arch/x86/isa/microops/fpop.isa
+++ b/src/arch/x86/isa/microops/fpop.isa
@@ -99,12 +99,12 @@ def template MicroFpOpDeclare {{
         %(class_name)s(ExtMachInst _machInst,
                 const char * instMnem,
                 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
-                RegIndex _src1, RegIndex _src2, RegIndex _dest,
+                InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
                 uint8_t _dataSize, int8_t _spm);
 
         %(class_name)s(ExtMachInst _machInst,
                 const char * instMnem,
-                RegIndex _src1, RegIndex _src2, RegIndex _dest,
+                InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
                 uint8_t _dataSize, int8_t _spm);
 
         %(BasicExecDeclare)s
@@ -120,7 +120,7 @@ def template MicroFpOpConstructor {{
 
     inline %(class_name)s::%(class_name)s(
             ExtMachInst machInst, const char * instMnem,
-            RegIndex _src1, RegIndex _src2, RegIndex _dest,
+            InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
             uint8_t _dataSize, int8_t _spm) :
         %(base_class)s(machInst, "%(mnemonic)s", instMnem,
                 false, false, false, false,
@@ -133,7 +133,7 @@ def template MicroFpOpConstructor {{
     inline %(class_name)s::%(class_name)s(
             ExtMachInst machInst, const char * instMnem,
             bool isMicro, bool isDelayed, bool isFirst, bool isLast,
-            RegIndex _src1, RegIndex _src2, RegIndex _dest,
+            InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
             uint8_t _dataSize, int8_t _spm) :
         %(base_class)s(machInst, "%(mnemonic)s", instMnem,
                 isMicro, isDelayed, isFirst, isLast,
@@ -256,9 +256,9 @@ let {{
                 "spm" : self.spm}
 
     class Movfp(FpOp):
-        def __init__(self, dest, src1, flags=0, spm=0, \
+        def __init__(self, dest, src1, spm=0, \
                 SetStatus=False, dataSize="env.dataSize"):
-            super(Movfp, self).__init__(dest, src1, flags, \
+            super(Movfp, self).__init__(dest, src1, "InstRegIndex(0)", \
                     spm, SetStatus, dataSize)
         code = 'FpDestReg.uqw = FpSrcReg1.uqw;'
         else_code = 'FpDestReg.uqw = FpDestReg.uqw;'
@@ -274,7 +274,8 @@ let {{
     class ConvOp(FpOp):
         abstract = True
         def __init__(self, dest, src1):
-            super(ConvOp, self).__init__(dest, src1, "(int)FLOATREG_MICROFP0")
+            super(ConvOp, self).__init__(dest, src1, \
+                    "InstRegIndex(FLOATREG_MICROFP0)")
 
     # These probably shouldn't look at the ExtMachInst directly to figure
     # out what size to use and should instead delegate that to the macroop's
@@ -318,7 +319,7 @@ let {{
     class Compfp(FpOp):
         def __init__(self, src1, src2, spm=0, setStatus=False, \
                 dataSize="env.dataSize"):
-            super(Compfp, self).__init__("(int)FLOATREG_MICROFP0", \
+            super(Compfp, self).__init__("InstRegIndex(FLOATREG_MICROFP0)", \
                     src1, src2, spm, setStatus, dataSize)
         # This class sets the condition codes in rflags according to the
         # rules for comparing floating point.
diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa
index c4c57a954..94c707f73 100644
--- a/src/arch/x86/isa/microops/ldstop.isa
+++ b/src/arch/x86/isa/microops/ldstop.isa
@@ -121,17 +121,17 @@ def template MicroLeaDeclare {{
         %(class_name)s(ExtMachInst _machInst,
                 const char * instMnem,
                 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
-                uint8_t _scale, RegIndex _index, RegIndex _base,
-                uint64_t _disp, uint8_t _segment,
-                RegIndex _data,
+                uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
+                uint64_t _disp, InstRegIndex _segment,
+                InstRegIndex _data,
                 uint8_t _dataSize, uint8_t _addressSize,
                 Request::FlagsType _memFlags);
 
         %(class_name)s(ExtMachInst _machInst,
                 const char * instMnem,
-                uint8_t _scale, RegIndex _index, RegIndex _base,
-                uint64_t _disp, uint8_t _segment,
-                RegIndex _data,
+                uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
+                uint64_t _disp, InstRegIndex _segment,
+                InstRegIndex _data,
                 uint8_t _dataSize, uint8_t _addressSize,
                 Request::FlagsType _memFlags);
 
@@ -297,17 +297,17 @@ def template MicroLdStOpDeclare {{
         %(class_name)s(ExtMachInst _machInst,
                 const char * instMnem,
                 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
-                uint8_t _scale, RegIndex _index, RegIndex _base,
-                uint64_t _disp, uint8_t _segment,
-                RegIndex _data,
+                uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
+                uint64_t _disp, InstRegIndex _segment,
+                InstRegIndex _data,
                 uint8_t _dataSize, uint8_t _addressSize,
                 Request::FlagsType _memFlags);
 
         %(class_name)s(ExtMachInst _machInst,
                 const char * instMnem,
-                uint8_t _scale, RegIndex _index, RegIndex _base,
-                uint64_t _disp, uint8_t _segment,
-                RegIndex _data,
+                uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
+                uint64_t _disp, InstRegIndex _segment,
+                InstRegIndex _data,
                 uint8_t _dataSize, uint8_t _addressSize,
                 Request::FlagsType _memFlags);
 
@@ -328,9 +328,9 @@ def template MicroLdStOpConstructor {{
 
     inline %(class_name)s::%(class_name)s(
             ExtMachInst machInst, const char * instMnem,
-            uint8_t _scale, RegIndex _index, RegIndex _base,
-            uint64_t _disp, uint8_t _segment,
-            RegIndex _data,
+            uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
+            uint64_t _disp, InstRegIndex _segment,
+            InstRegIndex _data,
             uint8_t _dataSize, uint8_t _addressSize,
             Request::FlagsType _memFlags) :
         %(base_class)s(machInst, "%(mnemonic)s", instMnem,
@@ -345,9 +345,9 @@ def template MicroLdStOpConstructor {{
     inline %(class_name)s::%(class_name)s(
             ExtMachInst machInst, const char * instMnem,
             bool isMicro, bool isDelayed, bool isFirst, bool isLast,
-            uint8_t _scale, RegIndex _index, RegIndex _base,
-            uint64_t _disp, uint8_t _segment,
-            RegIndex _data,
+            uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
+            uint64_t _disp, InstRegIndex _segment,
+            InstRegIndex _data,
             uint8_t _dataSize, uint8_t _addressSize,
             Request::FlagsType _memFlags) :
         %(base_class)s(machInst, "%(mnemonic)s", instMnem,
@@ -517,7 +517,7 @@ let {{
         def __init__(self, segment, addr, disp = 0,
                 dataSize="env.dataSize",
                 addressSize="env.addressSize"):
-            super(TiaOp, self).__init__("NUM_INTREGS", segment,
+            super(TiaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment,
                     addr, disp, dataSize, addressSize, "0", False, False)
             self.className = "Tia"
             self.mnemonic = "tia"
@@ -528,7 +528,7 @@ let {{
         def __init__(self, segment, addr, disp = 0,
                 dataSize="env.dataSize",
                 addressSize="env.addressSize", atCPL0=False):
-            super(CdaOp, self).__init__("NUM_INTREGS", segment,
+            super(CdaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment,
                     addr, disp, dataSize, addressSize, "0", atCPL0, False)
             self.className = "Cda"
             self.mnemonic = "cda"
diff --git a/src/arch/x86/isa/microops/limmop.isa b/src/arch/x86/isa/microops/limmop.isa
index 4e75ab8b0..f7e7728ab 100644
--- a/src/arch/x86/isa/microops/limmop.isa
+++ b/src/arch/x86/isa/microops/limmop.isa
@@ -88,11 +88,11 @@ def template MicroLimmOpDeclare {{
         %(class_name)s(ExtMachInst _machInst,
                 const char * instMnem,
                 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
-                RegIndex _dest, uint64_t _imm, uint8_t _dataSize);
+                InstRegIndex _dest, uint64_t _imm, uint8_t _dataSize);
 
         %(class_name)s(ExtMachInst _machInst,
                 const char * instMnem,
-                RegIndex _dest, uint64_t _imm, uint8_t _dataSize);
+                InstRegIndex _dest, uint64_t _imm, uint8_t _dataSize);
 
         %(BasicExecDeclare)s
     };
@@ -122,10 +122,10 @@ def template MicroLimmOpConstructor {{
 
     inline %(class_name)s::%(class_name)s(
             ExtMachInst machInst, const char * instMnem,
-            RegIndex _dest, uint64_t _imm, uint8_t _dataSize) :
+            InstRegIndex _dest, uint64_t _imm, uint8_t _dataSize) :
         %(base_class)s(machInst, "%(mnemonic)s", instMnem,
                 false, false, false, false, %(op_class)s),
-                dest(_dest), imm(_imm), dataSize(_dataSize)
+                dest(_dest.idx), imm(_imm), dataSize(_dataSize)
     {
         buildMe();
     }
@@ -133,10 +133,10 @@ def template MicroLimmOpConstructor {{
     inline %(class_name)s::%(class_name)s(
             ExtMachInst machInst, const char * instMnem,
             bool isMicro, bool isDelayed, bool isFirst, bool isLast,
-            RegIndex _dest, uint64_t _imm, uint8_t _dataSize) :
+            InstRegIndex _dest, uint64_t _imm, uint8_t _dataSize) :
         %(base_class)s(machInst, "%(mnemonic)s", instMnem,
                 isMicro, isDelayed, isFirst, isLast, %(op_class)s),
-                dest(_dest), imm(_imm), dataSize(_dataSize)
+                dest(_dest.idx), imm(_imm), dataSize(_dataSize)
     {
         buildMe();
     }
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index dfa10587a..cabdc2172 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -126,12 +126,12 @@ def template MicroRegOpDeclare {{
         %(class_name)s(ExtMachInst _machInst,
                 const char * instMnem,
                 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
-                RegIndex _src1, RegIndex _src2, RegIndex _dest,
+                InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
                 uint8_t _dataSize, uint16_t _ext);
 
         %(class_name)s(ExtMachInst _machInst,
                 const char * instMnem,
-                RegIndex _src1, RegIndex _src2, RegIndex _dest,
+                InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
                 uint8_t _dataSize, uint16_t _ext);
 
         %(BasicExecDeclare)s
@@ -149,12 +149,12 @@ def template MicroRegOpImmDeclare {{
         %(class_name)s(ExtMachInst _machInst,
                 const char * instMnem,
                 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
-                RegIndex _src1, uint16_t _imm8, RegIndex _dest,
+                InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest,
                 uint8_t _dataSize, uint16_t _ext);
 
         %(class_name)s(ExtMachInst _machInst,
                 const char * instMnem,
-                RegIndex _src1, uint16_t _imm8, RegIndex _dest,
+                InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest,
                 uint8_t _dataSize, uint16_t _ext);
 
         %(BasicExecDeclare)s
@@ -170,7 +170,7 @@ def template MicroRegOpConstructor {{
 
     inline %(class_name)s::%(class_name)s(
             ExtMachInst machInst, const char * instMnem,
-            RegIndex _src1, RegIndex _src2, RegIndex _dest,
+            InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
             uint8_t _dataSize, uint16_t _ext) :
         %(base_class)s(machInst, "%(mnemonic)s", instMnem,
                 false, false, false, false,
@@ -183,7 +183,7 @@ def template MicroRegOpConstructor {{
     inline %(class_name)s::%(class_name)s(
             ExtMachInst machInst, const char * instMnem,
             bool isMicro, bool isDelayed, bool isFirst, bool isLast,
-            RegIndex _src1, RegIndex _src2, RegIndex _dest,
+            InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
             uint8_t _dataSize, uint16_t _ext) :
         %(base_class)s(machInst, "%(mnemonic)s", instMnem,
                 isMicro, isDelayed, isFirst, isLast,
@@ -203,7 +203,7 @@ def template MicroRegOpImmConstructor {{
 
     inline %(class_name)s::%(class_name)s(
             ExtMachInst machInst, const char * instMnem,
-            RegIndex _src1, uint16_t _imm8, RegIndex _dest,
+            InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest,
             uint8_t _dataSize, uint16_t _ext) :
         %(base_class)s(machInst, "%(mnemonic)s", instMnem,
                 false, false, false, false,
@@ -216,7 +216,7 @@ def template MicroRegOpImmConstructor {{
     inline %(class_name)s::%(class_name)s(
             ExtMachInst machInst, const char * instMnem,
             bool isMicro, bool isDelayed, bool isFirst, bool isLast,
-            RegIndex _src1, uint16_t _imm8, RegIndex _dest,
+            InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest,
             uint8_t _dataSize, uint16_t _ext) :
         %(base_class)s(machInst, "%(mnemonic)s", instMnem,
                 isMicro, isDelayed, isFirst, isLast,
@@ -481,12 +481,14 @@ let {{
         def __init__(self, dest, src1=None, dataSize="env.dataSize"):
             if not src1:
                 src1 = dest
-            super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize)
+            super(RdRegOp, self).__init__(dest, src1, \
+                    "InstRegIndex(NUM_INTREGS)", None, dataSize)
 
     class WrRegOp(RegOp):
         abstract = True
         def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
-            super(WrRegOp, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize)
+            super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \
+                    src1, src2, flags, dataSize)
 
     class Add(FlagRegOp):
         code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);'
@@ -553,7 +555,8 @@ let {{
         def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"):
             if not src1:
                 src1 = dest
-            super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", flags, dataSize)
+            super(RdRegOp, self).__init__(dest, src1, \
+                    "InstRegIndex(NUM_INTREGS)", flags, dataSize)
         code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);'
         flag_code = '''
             if (ProdHi)
@@ -885,7 +888,7 @@ let {{
         def __init__(self, dest, imm, flags=None, \
                 dataSize="env.dataSize"):
             super(Ruflag, self).__init__(dest, \
-                    "NUM_INTREGS", imm, flags, dataSize)
+                    "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize)
 
     class Rflag(RegOp):
         code = '''
@@ -899,7 +902,7 @@ let {{
         def __init__(self, dest, imm, flags=None, \
                 dataSize="env.dataSize"):
             super(Rflag, self).__init__(dest, \
-                    "NUM_INTREGS", imm, flags, dataSize)
+                    "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize)
 
     class Sext(RegOp):
         code = '''
@@ -926,7 +929,7 @@ let {{
     class Rddr(RegOp):
         def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
             super(Rddr, self).__init__(dest, \
-                    src1, "NUM_INTREGS", flags, dataSize)
+                    src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
         code = '''
             CR4 cr4 = CR4Op;
             DR7 dr7 = DR7Op;
@@ -942,14 +945,13 @@ let {{
     class Wrdr(RegOp):
         def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
             super(Wrdr, self).__init__(dest, \
-                    src1, "NUM_INTREGS", flags, dataSize)
+                    src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
         code = '''
             CR4 cr4 = CR4Op;
             DR7 dr7 = DR7Op;
             if ((cr4.de == 1 && (dest == 4 || dest == 5)) || dest >= 8) {
                 fault = new InvalidOpcode();
-            } else if ((dest == 6 || dest == 7) &&
-                    bits(psrc1, 63, 32) &&
+            } else if ((dest == 6 || dest == 7) && bits(psrc1, 63, 32) &&
                     machInst.mode.mode == LongMode) {
                 fault = new GeneralProtection(0);
             } else if (dr7.gd) {
@@ -962,7 +964,7 @@ let {{
     class Rdcr(RegOp):
         def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
             super(Rdcr, self).__init__(dest, \
-                    src1, "NUM_INTREGS", flags, dataSize)
+                    src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
         code = '''
             if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) {
                 fault = new InvalidOpcode();
@@ -974,7 +976,7 @@ let {{
     class Wrcr(RegOp):
         def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
             super(Wrcr, self).__init__(dest, \
-                    src1, "NUM_INTREGS", flags, dataSize)
+                    src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
         code = '''
             if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) {
                 fault = new InvalidOpcode();
@@ -1028,7 +1030,7 @@ let {{
         abstract = True
         def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
             super(SegOp, self).__init__(dest, \
-                    src1, "NUM_INTREGS", flags, dataSize)
+                    src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
 
     class Wrbase(SegOp):
         code = '''
@@ -1072,16 +1074,16 @@ let {{
 
     class Rdval(RegOp):
         def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
-            super(Rdval, self).__init__(dest, \
-                    src1, "NUM_INTREGS", flags, dataSize)
+            super(Rdval, self).__init__(dest, src1, \
+                    "InstRegIndex(NUM_INTREGS)", flags, dataSize)
         code = '''
             DestReg = MiscRegSrc1;
         '''
 
     class Wrval(RegOp):
         def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
-            super(Wrval, self).__init__(dest, \
-                    src1, "NUM_INTREGS", flags, dataSize)
+            super(Wrval, self).__init__(dest, src1, \
+                    "InstRegIndex(NUM_INTREGS)", flags, dataSize)
         code = '''
             MiscRegDest = SrcReg1;
         '''
diff --git a/src/arch/x86/miscregs.hh b/src/arch/x86/miscregs.hh
index 106996848..2dc4587e3 100644
--- a/src/arch/x86/miscregs.hh
+++ b/src/arch/x86/miscregs.hh
@@ -165,8 +165,9 @@ namespace X86ISA
         MISCREG_MTRR_PHYS_BASE_5,
         MISCREG_MTRR_PHYS_BASE_6,
         MISCREG_MTRR_PHYS_BASE_7,
+        MISCREG_MTRR_PHYS_BASE_END,
 
-        MISCREG_MTRR_PHYS_MASK_BASE,
+        MISCREG_MTRR_PHYS_MASK_BASE = MISCREG_MTRR_PHYS_BASE_END,
         MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE,
         MISCREG_MTRR_PHYS_MASK_1,
         MISCREG_MTRR_PHYS_MASK_2,
@@ -175,8 +176,9 @@ namespace X86ISA
         MISCREG_MTRR_PHYS_MASK_5,
         MISCREG_MTRR_PHYS_MASK_6,
         MISCREG_MTRR_PHYS_MASK_7,
+        MISCREG_MTRR_PHYS_MASK_END,
 
-        MISCREG_MTRR_FIX_64K_00000,
+        MISCREG_MTRR_FIX_64K_00000 = MISCREG_MTRR_PHYS_MASK_END,
         MISCREG_MTRR_FIX_16K_80000,
         MISCREG_MTRR_FIX_16K_A0000,
         MISCREG_MTRR_FIX_4K_C0000,
@@ -201,8 +203,9 @@ namespace X86ISA
         MISCREG_MC5_CTL,
         MISCREG_MC6_CTL,
         MISCREG_MC7_CTL,
+        MISCREG_MC_CTL_END,
 
-        MISCREG_MC_STATUS_BASE,
+        MISCREG_MC_STATUS_BASE = MISCREG_MC_CTL_END,
         MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE,
         MISCREG_MC1_STATUS,
         MISCREG_MC2_STATUS,
@@ -211,8 +214,9 @@ namespace X86ISA
         MISCREG_MC5_STATUS,
         MISCREG_MC6_STATUS,
         MISCREG_MC7_STATUS,
+        MISCREG_MC_STATUS_END,
 
-        MISCREG_MC_ADDR_BASE,
+        MISCREG_MC_ADDR_BASE = MISCREG_MC_STATUS_END,
         MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE,
         MISCREG_MC1_ADDR,
         MISCREG_MC2_ADDR,
@@ -221,8 +225,9 @@ namespace X86ISA
         MISCREG_MC5_ADDR,
         MISCREG_MC6_ADDR,
         MISCREG_MC7_ADDR,
+        MISCREG_MC_ADDR_END,
 
-        MISCREG_MC_MISC_BASE,
+        MISCREG_MC_MISC_BASE = MISCREG_MC_ADDR_END,
         MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE,
         MISCREG_MC1_MISC,
         MISCREG_MC2_MISC,
@@ -231,9 +236,10 @@ namespace X86ISA
         MISCREG_MC5_MISC,
         MISCREG_MC6_MISC,
         MISCREG_MC7_MISC,
+        MISCREG_MC_MISC_END,
 
         // Extended feature enable register
-        MISCREG_EFER,
+        MISCREG_EFER = MISCREG_MC_MISC_END,
 
         MISCREG_STAR,
         MISCREG_LSTAR,
@@ -250,24 +256,28 @@ namespace X86ISA
         MISCREG_PERF_EVT_SEL1,
         MISCREG_PERF_EVT_SEL2,
         MISCREG_PERF_EVT_SEL3,
+        MISCREG_PERF_EVT_SEL_END,
 
-        MISCREG_PERF_EVT_CTR_BASE,
+        MISCREG_PERF_EVT_CTR_BASE = MISCREG_PERF_EVT_SEL_END,
         MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE,
         MISCREG_PERF_EVT_CTR1,
         MISCREG_PERF_EVT_CTR2,
         MISCREG_PERF_EVT_CTR3,
+        MISCREG_PERF_EVT_CTR_END,
 
-        MISCREG_SYSCFG,
+        MISCREG_SYSCFG = MISCREG_PERF_EVT_CTR_END,
 
         MISCREG_IORR_BASE_BASE,
         MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE,
         MISCREG_IORR_BASE1,
+        MISCREG_IORR_BASE_END,
 
-        MISCREG_IORR_MASK_BASE,
+        MISCREG_IORR_MASK_BASE = MISCREG_IORR_BASE_END,
         MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE,
         MISCREG_IORR_MASK1,
+        MISCREG_IORR_MASK_END,
 
-        MISCREG_TOP_MEM,
+        MISCREG_TOP_MEM = MISCREG_IORR_MASK_END,
         MISCREG_TOP_MEM2,
 
         MISCREG_VM_CR,
@@ -377,102 +387,129 @@ namespace X86ISA
     static inline MiscRegIndex
     MISCREG_CR(int index)
     {
+        assert(index >= 0 && index < NumCRegs);
         return (MiscRegIndex)(MISCREG_CR_BASE + index);
     }
 
     static inline MiscRegIndex
     MISCREG_DR(int index)
     {
+        assert(index >= 0 && index < NumDRegs);
         return (MiscRegIndex)(MISCREG_DR_BASE + index);
     }
 
     static inline MiscRegIndex
     MISCREG_MTRR_PHYS_BASE(int index)
     {
+        assert(index >= 0 && index < (MISCREG_MTRR_PHYS_BASE_END -
+                                      MISCREG_MTRR_PHYS_BASE_BASE));
         return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index);
     }
 
     static inline MiscRegIndex
     MISCREG_MTRR_PHYS_MASK(int index)
     {
+        assert(index >= 0 && index < (MISCREG_MTRR_PHYS_MASK_END -
+                                      MISCREG_MTRR_PHYS_MASK_BASE));
         return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index);
     }
 
     static inline MiscRegIndex
     MISCREG_MC_CTL(int index)
     {
+        assert(index >= 0 && index < (MISCREG_MC_CTL_END -
+                                      MISCREG_MC_CTL_BASE));
         return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index);
     }
 
     static inline MiscRegIndex
     MISCREG_MC_STATUS(int index)
     {
+        assert(index >= 0 && index < (MISCREG_MC_STATUS_END -
+                                      MISCREG_MC_STATUS_BASE));
         return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index);
     }
 
     static inline MiscRegIndex
     MISCREG_MC_ADDR(int index)
     {
+        assert(index >= 0 && index < (MISCREG_MC_ADDR_END -
+                                      MISCREG_MC_ADDR_BASE));
         return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index);
     }
 
     static inline MiscRegIndex
     MISCREG_MC_MISC(int index)
     {
+        assert(index >= 0 && index < (MISCREG_MC_MISC_END -
+                                      MISCREG_MC_MISC_BASE));
         return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index);
     }
 
     static inline MiscRegIndex
     MISCREG_PERF_EVT_SEL(int index)
     {
+        assert(index >= 0 && index < (MISCREG_PERF_EVT_SEL_END -
+                                      MISCREG_PERF_EVT_SEL_BASE));
         return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index);
     }
 
     static inline MiscRegIndex
     MISCREG_PERF_EVT_CTR(int index)
     {
+        assert(index >= 0 && index < (MISCREG_PERF_EVT_CTR_END -
+                                      MISCREG_PERF_EVT_CTR_BASE));
         return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index);
     }
 
     static inline MiscRegIndex
     MISCREG_IORR_BASE(int index)
     {
+        assert(index >= 0 && index < (MISCREG_IORR_BASE_END -
+                                      MISCREG_IORR_BASE_BASE));
         return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index);
     }
 
     static inline MiscRegIndex
     MISCREG_IORR_MASK(int index)
     {
+        assert(index >= 0 && index < (MISCREG_IORR_MASK_END -
+                                      MISCREG_IORR_MASK_BASE));
         return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index);
     }
 
     static inline MiscRegIndex
     MISCREG_SEG_SEL(int index)
     {
+        assert(index >= 0 && index < NUM_SEGMENTREGS);
         return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index);
     }
 
     static inline MiscRegIndex
     MISCREG_SEG_BASE(int index)
     {
+        assert(index >= 0 && index < NUM_SEGMENTREGS);
         return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index);
     }
 
     static inline MiscRegIndex
     MISCREG_SEG_EFF_BASE(int index)
     {
+        assert(index >= 0 && index < NUM_SEGMENTREGS);
         return (MiscRegIndex)(MISCREG_SEG_EFF_BASE_BASE + index);
     }
 
     static inline MiscRegIndex
     MISCREG_SEG_LIMIT(int index)
     {
+        assert(index >= 0 && index < NUM_SEGMENTREGS);
         return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index);
     }
 
     static inline MiscRegIndex
     MISCREG_SEG_ATTR(int index)
     {
+        assert(index >= 0 && index < NUM_SEGMENTREGS);
         return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index);
     }