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authorAli Saidi <Ali.Saidi@ARM.com>2010-12-07 16:19:57 -0800
committerAli Saidi <Ali.Saidi@ARM.com>2010-12-07 16:19:57 -0800
commit21bfbd422cb9d043f88bd7f5ca9d4c72b97f9f33 (patch)
tree8daca00e0dc933e7442da1eb7a017fe2be8734fe /src/arch
parent658849d101c98b6d8c7a06f41ffbe39675848eac (diff)
downloadgem5-21bfbd422cb9d043f88bd7f5ca9d4c72b97f9f33.tar.xz
ARM: Support switchover with hardware table walkers
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/table_walker.cc3
-rw-r--r--src/arch/arm/tlb.cc12
-rw-r--r--src/arch/arm/tlb.hh3
3 files changed, 16 insertions, 2 deletions
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 98dc1760d..88f2a455f 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -92,8 +92,7 @@ TableWalker::getPort(const std::string &if_name, int idx)
{
if (if_name == "port") {
if (port != NULL)
- fatal("%s: port already connected to %s",
- name(), port->getPeer()->name());
+ return port;
System *sys = params()->sys;
Tick minb = params()->min_backoff;
Tick maxb = params()->max_backoff;
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 6d6da15c8..f142e03f8 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -693,6 +693,18 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
return fault;
}
+Port*
+TLB::getPort()
+{
+#if FULL_SYSTEM
+ return tableWalker->getPort("port");
+#else
+ return NULL;
+#endif
+}
+
+
+
ArmISA::TLB *
ArmTLBParams::create()
{
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 0b8bc1046..21062ea0d 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -209,6 +209,9 @@ class TLB : public BaseTLB
void regStats();
+ // Get the port from the table walker and return it
+ virtual Port *getPort();
+
// Caching misc register values here.
// Writing to misc registers needs to invalidate them.
// translateFunctional/translateSe/translateFs checks if they are