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authorGabe Black <gblack@eecs.umich.edu>2007-02-22 13:17:51 +0000
committerGabe Black <gblack@eecs.umich.edu>2007-02-22 13:17:51 +0000
commit34b4722aeeb5abdf34c3e90365411297884680fe (patch)
treebe51bfb3fac956e5a8e5585b3786046a21f8f93c /src/arch
parent783e642ed8cf45e65ddb7a47f5bd2c34df1900cd (diff)
downloadgem5-34b4722aeeb5abdf34c3e90365411297884680fe.tar.xz
Make the m5 pseudo instructions only work in FS. Also, make sure any undefined opcodes in impdep2 (which in SE is all of them) trap with an illegal_instruction exception.
--HG-- extra : convert_revision : dd7848d0685e4cc6f5fd5e3b846a3f70b62ee30a
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/sparc/isa/decoder.isa4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index e2d1707dd..2ce700ef1 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -1011,13 +1011,15 @@ decode OP default Unknown::unknown()
}
// M5 special opcodes use the reserved IMPDEP2A opcode space
0x37: decode M5FUNC {
+#if FULL_SYSTEM
// we have 7 bits of space here to play with...
0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0);
}}, No_OpClass, IsNonSpeculative);
0x54: m5panic({{
panic("M5 panic instruction called at pc=%#x.", xc->readPC());
}}, No_OpClass, IsNonSpeculative);
-
+#endif
+ default: Trap::impdep2({{fault = new IllegalInstruction;}});
}
0x38: Branch::jmpl({{
Addr target = Rs1 + Rs2_or_imm13;