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authorGabe Black <gblack@eecs.umich.edu>2009-07-01 22:11:54 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-07-01 22:11:54 -0700
commit4f98171479c8b9f8544665a19520e279fcd30f5b (patch)
tree087b117a27c3a3545720f475fcd6fc45f1146562 /src/arch
parentb8f064c88c48c549987a13eb4f4350bc6745ab15 (diff)
downloadgem5-4f98171479c8b9f8544665a19520e279fcd30f5b.tar.xz
ARM: Decode some media instructions. These are untested.
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/isa/bitfields.isa2
-rw-r--r--src/arch/arm/isa/decoder.isa54
-rw-r--r--src/arch/arm/types.hh1
3 files changed, 57 insertions, 0 deletions
diff --git a/src/arch/arm/isa/bitfields.isa b/src/arch/arm/isa/bitfields.isa
index 37b84e282..c9f15ff59 100644
--- a/src/arch/arm/isa/bitfields.isa
+++ b/src/arch/arm/isa/bitfields.isa
@@ -37,6 +37,8 @@
def bitfield ENCODING encoding;
def bitfield OPCODE opcode;
def bitfield OPCODE_24_23 opcode24_23;
+def bitfield MEDIA_OPCODE mediaOpcode;
+def bitfield MEDIA_OPCODE2 mediaOpcode2;
def bitfield OPCODE_24 opcode24;
def bitfield OPCODE_23_20 opcode23_20;
def bitfield OPCODE_23_21 opcode23_21;
diff --git a/src/arch/arm/isa/decoder.isa b/src/arch/arm/isa/decoder.isa
index c43a550a7..e0715312b 100644
--- a/src/arch/arm/isa/decoder.isa
+++ b/src/arch/arm/isa/decoder.isa
@@ -566,6 +566,60 @@ format DataOp {
Rn = Rn + Rm_Imm; }},
{{ EA = Rn + Rm_Imm; }});
}
+ 1: decode MEDIA_OPCODE {
+ 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7: WarnUnimpl::parallel_add_subtract_instructions();
+ 0x8: decode MISC_OPCODE {
+ 0x1, 0x9: WarnUnimpl::pkhbt();
+ 0x7: WarnUnimpl::sxtab16();
+ 0xb: WarnUnimpl::sel();
+ 0x5, 0xd: WarnUnimpl::pkhtb();
+ 0x3: WarnUnimpl::sign_zero_extend_add();
+ }
+ 0xa, 0xb: decode SHIFT {
+ 0x0, 0x2: WarnUnimpl::ssat();
+ 0x1: WarnUnimpl::ssat16();
+ }
+ 0xe, 0xf: decode SHIFT {
+ 0x0, 0x2: WarnUnimpl::usat();
+ 0x1: WarnUnimpl::usat16();
+ }
+ 0x10: decode RN {
+ 0xf: decode MISC_OPCODE {
+ 0x1: WarnUnimpl::smuad();
+ 0x3: WarnUnimpl::smuadx();
+ 0x5: WarnUnimpl::smusd();
+ 0x7: WarnUnimpl::smusdx();
+ }
+ default: decode MISC_OPCODE {
+ 0x1: WarnUnimpl::smlad();
+ 0x3: WarnUnimpl::smladx();
+ 0x5: WarnUnimpl::smlsd();
+ 0x7: WarnUnimpl::smlsdx();
+ }
+ }
+ 0x14: decode MISC_OPCODE {
+ 0x1: WarnUnimpl::smlald();
+ 0x3: WarnUnimpl::smlaldx();
+ 0x5: WarnUnimpl::smlsld();
+ 0x7: WarnUnimpl::smlsldx();
+ }
+ 0x15: decode RN {
+ 0xf: decode MISC_OPCODE {
+ 0x1: WarnUnimpl::smmul();
+ 0x3: WarnUnimpl::smmulr();
+ }
+ default: decode MISC_OPCODE {
+ 0x1: WarnUnimpl::smmla();
+ 0x3: WarnUnimpl::smmlar();
+ 0xd: WarnUnimpl::smmls();
+ 0xf: WarnUnimpl::smmlsr();
+ }
+ }
+ 0x18: decode RN {
+ 0xf: WarnUnimpl::usada8();
+ default: WarnUnimpl::usad8();
+ }
+ }
}
0x4: decode PUSWL {
// Right now we only handle cases when S (PSRUSER) is not set
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index cff6b123c..707d7d0f6 100644
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -46,6 +46,7 @@ namespace ArmISA
// All the different types of opcode fields.
Bitfield<27, 25> encoding;
Bitfield<24, 21> opcode;
+ Bitfield<24, 20> mediaOpcode;
Bitfield<24, 23> opcode24_23;
Bitfield<24> opcode24;
Bitfield<23, 20> opcode23_20;