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authorGabe Black <gblack@eecs.umich.edu>2010-08-13 06:10:45 -0700
committerGabe Black <gblack@eecs.umich.edu>2010-08-13 06:10:45 -0700
commit52a90a5998bf353a8add0e90c50dc934f18cff82 (patch)
tree9db25795dfdc70511038885d11c8eb5d641b0946 /src/arch
parent2e9e75447a50146e0e8346de4362f7a4570f84ec (diff)
downloadgem5-52a90a5998bf353a8add0e90c50dc934f18cff82.tar.xz
CPU: Tidy up endianness handling for mmapped "IPR"s.
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/sparc/tlb.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 41b0f2043..9d3b22657 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -1049,7 +1049,7 @@ doMmuReadError:
Tick
TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
{
- uint64_t data = gtoh(pkt->get<uint64_t>());
+ uint64_t data = pkt->get<uint64_t>();
Addr va = pkt->getAddr();
ASI asi = (ASI)pkt->req->getAsi();