summaryrefslogtreecommitdiff
path: root/src/arch
diff options
context:
space:
mode:
authorMatt Horsnell <Matt.Horsnell@arm.com>2011-01-18 16:30:02 -0600
committerMatt Horsnell <Matt.Horsnell@arm.com>2011-01-18 16:30:02 -0600
commit5ebf3b280867925917654f5362d3ece21dc2355e (patch)
treefb57127c839ef57d0f2dfa1b11b35fbdb7225dd4 /src/arch
parentee9a331fe59356a11e6f610967cd5aa08cef3db9 (diff)
downloadgem5-5ebf3b280867925917654f5362d3ece21dc2355e.tar.xz
O3: Fixes the way prefetches are handled inside the iew unit.
This patch prevents the prefetch being added to the instCommit queue twice.
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/faults.hh3
-rw-r--r--src/arch/arm/tlb.cc8
2 files changed, 9 insertions, 2 deletions
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 6c1b223ab..633e74eae 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -92,7 +92,8 @@ class ArmFault : public FaultBase
// to allow the translation function to inform
// the memory access function not to proceed
// for a Prefetch that misses in the TLB.
- PrefetchTLBMiss
+ PrefetchTLBMiss = 0x1f,
+ PrefetchUncacheable = 0x20
};
struct FaultVals
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index f142e03f8..e5f5b36f6 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -556,9 +556,15 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
outerAttrs: %d\n",
te->shareable, te->innerAttrs, te->outerAttrs);
setAttr(te->attributes);
- if (te->nonCacheable)
+ if (te->nonCacheable) {
req->setFlags(Request::UNCACHEABLE);
+ // Prevent prefetching from I/O devices.
+ if (req->isPrefetch()) {
+ return new PrefetchAbort(vaddr, ArmFault::PrefetchUncacheable);
+ }
+ }
+
switch ( (dacr >> (te->domain * 2)) & 0x3) {
case 0:
domainFaults++;