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authorAli Saidi <Ali.Saidi@ARM.com>2014-01-24 15:29:30 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2014-01-24 15:29:30 -0600
commit6bed6e0352a68723ea55017b3e09a8c279af11ec (patch)
treef7fb2a163ea470144a424bf21a7dd578754546af /src/arch
parentd3444c6603afe38b00036292a854f52069b90a80 (diff)
downloadgem5-6bed6e0352a68723ea55017b3e09a8c279af11ec.tar.xz
cpu: Add CPU support for generatig wake up events when LLSC adresses are snooped.
This patch add support for generating wake-up events in the CPU when an address that is currently in the exclusive state is hit by a snoop. This mechanism is required for ARMv8 multi-processor support.
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/alpha/locked_mem.hh7
-rw-r--r--src/arch/arm/locked_mem.hh20
-rw-r--r--src/arch/mips/locked_mem.hh8
-rw-r--r--src/arch/power/locked_mem.hh8
-rw-r--r--src/arch/sparc/locked_mem.hh8
-rw-r--r--src/arch/x86/locked_mem.hh8
6 files changed, 46 insertions, 13 deletions
diff --git a/src/arch/alpha/locked_mem.hh b/src/arch/alpha/locked_mem.hh
index e62ed1654..253b94be4 100644
--- a/src/arch/alpha/locked_mem.hh
+++ b/src/arch/alpha/locked_mem.hh
@@ -93,10 +93,15 @@ handleLockedRead(XC *xc, Request *req)
xc->setMiscReg(MISCREG_LOCKFLAG, true);
}
+template <class XC>
+inline void
+handleLockedSnoopHit(XC *xc)
+{
+}
template <class XC>
inline bool
-handleLockedWrite(XC *xc, Request *req)
+handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
{
if (req->isUncacheable()) {
// Funky Turbolaser mailbox access...don't update
diff --git a/src/arch/arm/locked_mem.hh b/src/arch/arm/locked_mem.hh
index 37973ff98..f2601f00c 100644
--- a/src/arch/arm/locked_mem.hh
+++ b/src/arch/arm/locked_mem.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012-2013 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -66,9 +66,7 @@ handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
return;
Addr locked_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask;
- Addr snoop_addr = pkt->getAddr();
-
- assert((cacheBlockMask & snoop_addr) == snoop_addr);
+ Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
if (locked_addr == snoop_addr)
xc->setMiscReg(MISCREG_LOCKFLAG, false);
@@ -76,16 +74,22 @@ handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
template <class XC>
inline void
+handleLockedSnoopHit(XC *xc)
+{
+}
+
+template <class XC>
+inline void
handleLockedRead(XC *xc, Request *req)
{
- xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf);
+ xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr());
xc->setMiscReg(MISCREG_LOCKFLAG, true);
}
template <class XC>
inline bool
-handleLockedWrite(XC *xc, Request *req)
+handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
{
if (req->isSwap())
return true;
@@ -93,8 +97,8 @@ handleLockedWrite(XC *xc, Request *req)
// Verify that the lock flag is still set and the address
// is correct
bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG);
- Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR);
- if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
+ Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask;
+ if (!lock_flag || (req->getPaddr() & cacheBlockMask) != lock_addr) {
// Lock flag not set or addr mismatch in CPU;
// don't even bother sending to memory system
req->setExtraData(0);
diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh
index b4003fea9..5b0f8a1b8 100644
--- a/src/arch/mips/locked_mem.hh
+++ b/src/arch/mips/locked_mem.hh
@@ -87,8 +87,14 @@ handleLockedRead(XC *xc, Request *req)
}
template <class XC>
+inline void
+handleLockedSnoopHit(XC *xc)
+{
+}
+
+template <class XC>
inline bool
-handleLockedWrite(XC *xc, Request *req)
+handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
{
if (req->isUncacheable()) {
// Funky Turbolaser mailbox access...don't update
diff --git a/src/arch/power/locked_mem.hh b/src/arch/power/locked_mem.hh
index f3d042d5c..d962f9aff 100644
--- a/src/arch/power/locked_mem.hh
+++ b/src/arch/power/locked_mem.hh
@@ -60,8 +60,14 @@ handleLockedRead(XC *xc, Request *req)
}
template <class XC>
+inline void
+handleLockedSnoopHit(XC *xc)
+{
+}
+
+template <class XC>
inline bool
-handleLockedWrite(XC *xc, Request *req)
+handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
{
return true;
}
diff --git a/src/arch/sparc/locked_mem.hh b/src/arch/sparc/locked_mem.hh
index 8277ef487..b28179481 100644
--- a/src/arch/sparc/locked_mem.hh
+++ b/src/arch/sparc/locked_mem.hh
@@ -54,10 +54,16 @@ handleLockedRead(XC *xc, Request *req)
{
}
+template <class XC>
+inline void
+handleLockedSnoopHit(XC *xc)
+{
+}
+
template <class XC>
inline bool
-handleLockedWrite(XC *xc, Request *req)
+handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
{
return true;
}
diff --git a/src/arch/x86/locked_mem.hh b/src/arch/x86/locked_mem.hh
index c2a8395aa..51cfb2ea3 100644
--- a/src/arch/x86/locked_mem.hh
+++ b/src/arch/x86/locked_mem.hh
@@ -56,10 +56,16 @@ namespace X86ISA
template <class XC>
inline bool
- handleLockedWrite(XC *xc, Request *req)
+ handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
{
return true;
}
+
+ template <class XC>
+ inline void
+ handleLockedSnoopHit(XC *xc)
+ {
+ }
}
#endif // __ARCH_X86_LOCKEDMEM_HH__