MIPS: Get MIPS_FS to compile, more style fixes.

Some breakage was from my BitUnion change, some was much older.

9 files changed, 219 insertions, 194 deletions

diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc
index 01d31e14f..6faab054f 100644
--- a/src/arch/mips/faults.cc
+++ b/src/arch/mips/faults.cc
@@ -175,49 +175,44 @@ MipsFault::setHandlerPC(Addr HandlerBase, ThreadContext *tc)
 }
 
 void
-MipsFault::setExceptionState(ThreadContext *tc, uint8_t ExcCode)
+MipsFault::setExceptionState(ThreadContext *tc, uint8_t excCode)
 {
     // modify SRS Ctl - Save CSS, put ESS into CSS
-    MiscReg stat = tc->readMiscReg(MipsISA::Status);
-    if (bits(stat, Status_EXL) != 1 && bits(stat, Status_BEV) != 1) {
+    StatusReg status = tc->readMiscReg(Status);
+    if (status.exl != 1 && status.bev != 1) {
         // SRS Ctl is modified only if Status_EXL and Status_BEV are not set
-        MiscReg srs = tc->readMiscReg(MipsISA::SRSCtl);
-        uint8_t CSS, ESS;
-        CSS = bits(srs, SRSCtl_CSS_HI, SRSCtl_CSS_LO);
-        ESS = bits(srs, SRSCtl_ESS_HI, SRSCtl_ESS_LO);
-        // Move CSS to PSS
-        replaceBits(srs, SRSCtl_PSS_HI, SRSCtl_PSS_LO, CSS);
-        // Move ESS to CSS
-        replaceBits(srs, SRSCtl_CSS_HI, SRSCtl_CSS_LO, ESS);
-        tc->setMiscRegNoEffect(MipsISA::SRSCtl, srs);
+        SRSCtlReg srsCtl = tc->readMiscReg(SRSCtl);
+        srsCtl.pss = srsCtl.css;
+        srsCtl.css = srsCtl.ess;
+        tc->setMiscRegNoEffect(SRSCtl, srsCtl);
     }
 
     // set EXL bit (don't care if it is already set!)
-    replaceBits(stat, Status_EXL_HI, Status_EXL_LO, 1);
-    tc->setMiscRegNoEffect(MipsISA::Status, stat);
+    status.exl = 1;
+    tc->setMiscRegNoEffect(Status, status);
 
     // write EPC
     // CHECK ME  or FIXME or FIX ME or POSSIBLE HACK
     // Check to see if the exception occurred in the branch delay slot
     DPRINTF(MipsPRA, "PC: %x, NextPC: %x, NNPC: %x\n",
             tc->readPC(), tc->readNextPC(), tc->readNextNPC());
-    int C_BD = 0;
+    int bd = 0;
     if (tc->readPC() + sizeof(MachInst) != tc->readNextPC()) {
-        tc->setMiscRegNoEffect(MipsISA::EPC, tc->readPC() - sizeof(MachInst));
+        tc->setMiscRegNoEffect(EPC, tc->readPC() - sizeof(MachInst));
         // In the branch delay slot? set CAUSE_31
-        C_BD = 1;
+        bd = 1;
     } else {
-        tc->setMiscRegNoEffect(MipsISA::EPC, tc->readPC());
+        tc->setMiscRegNoEffect(EPC, tc->readPC());
         // In the branch delay slot? reset CAUSE_31
-        C_BD = 0;
+        bd = 0;
     }
 
     // Set Cause_EXCCODE field
-    MiscReg cause = tc->readMiscReg(MipsISA::Cause);
-    replaceBits(cause, Cause_EXCCODE_HI, Cause_EXCCODE_LO, ExcCode);
-    replaceBits(cause, Cause_BD_HI, Cause_BD_LO,C_BD);
-    replaceBits(cause, Cause_CE_HI, Cause_CE_LO,0);
-    tc->setMiscRegNoEffect(MipsISA::Cause, cause);
+    CauseReg cause = tc->readMiscReg(Cause);
+    cause.excCode = excCode;
+    cause.bd = bd;
+    cause.ce = 0;
+    tc->setMiscRegNoEffect(Cause, cause);
 }
 
 void
@@ -228,12 +223,12 @@ ArithmeticFault::invoke(ThreadContext *tc)
 
     // Set new PC
     Addr HandlerBase;
-    MiscReg stat = tc->readMiscReg(MipsISA::Status);
+    StatusReg status = tc->readMiscReg(Status);
     // Here, the handler is dependent on BEV, which is not modified by
     // setExceptionState()
-    if (bits(stat, Status_BEV) == 0 ) {
+    if (!status.bev) {
         // See MIPS ARM Vol 3, Revision 2, Page 38
-        HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
+        HandlerBase = vect() + tc->readMiscReg(EBase);
     } else {
         HandlerBase = 0xBFC00200;
     }
@@ -245,12 +240,12 @@ StoreAddressErrorFault::invoke(ThreadContext *tc)
 {
     DPRINTF(MipsPRA, "%s encountered.\n", name());
     setExceptionState(tc, 0x5);
-    tc->setMiscRegNoEffect(MipsISA::BadVAddr, BadVAddr);
+    tc->setMiscRegNoEffect(BadVAddr, badVAddr);
 
     // Set new PC
     Addr HandlerBase;
     // Offset 0x180 - General Exception Vector
-    HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
+    HandlerBase = vect() + tc->readMiscReg(EBase);
     setHandlerPC(HandlerBase, tc);
 }
 
@@ -263,7 +258,7 @@ TrapFault::invoke(ThreadContext *tc)
     // Set new PC
     Addr HandlerBase;
     // Offset 0x180 - General Exception Vector
-    HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
+    HandlerBase = vect() + tc->readMiscReg(EBase);
     setHandlerPC(HandlerBase, tc);
 }
 
@@ -275,7 +270,7 @@ BreakpointFault::invoke(ThreadContext *tc)
     // Set new PC
     Addr HandlerBase;
     // Offset 0x180 - General Exception Vector
-    HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
+    HandlerBase = vect() + tc->readMiscReg(EBase);
     setHandlerPC(HandlerBase, tc);
 }
 
@@ -284,23 +279,24 @@ DtbInvalidFault::invoke(ThreadContext *tc)
 {
     DPRINTF(MipsPRA, "%s encountered.\n", name());
 
-    tc->setMiscRegNoEffect(MipsISA::BadVAddr, BadVAddr);
-    MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
-    replaceBits(eh, EntryHi_ASID_HI, EntryHi_ASID_LO, EntryHi_Asid);
-    replaceBits(eh, EntryHi_VPN2_HI, EntryHi_VPN2_LO, EntryHi_VPN2);
-    replaceBits(eh, EntryHi_VPN2X_HI, EntryHi_VPN2X_LO, EntryHi_VPN2X);
-    tc->setMiscRegNoEffect(MipsISA::EntryHi, eh);
-    MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
-    replaceBits(ctxt, Context_BadVPN2_HI, Context_BadVPN2_LO, Context_BadVPN2);
-    tc->setMiscRegNoEffect(MipsISA::Context, ctxt);
+    tc->setMiscRegNoEffect(BadVAddr, badVAddr);
+    EntryHiReg entryHi = tc->readMiscReg(EntryHi);
+    entryHi.asid = entryHiAsid;
+    entryHi.vpn2 = entryHiVPN2;
+    entryHi.vpn2x = entryHiVPN2X;
+    tc->setMiscRegNoEffect(EntryHi, entryHi);
+
+    ContextReg context = tc->readMiscReg(Context);
+    context.badVPN2 = contextBadVPN2;
+    tc->setMiscRegNoEffect(Context, context);
     setExceptionState(tc, 0x3);
 
 
     // Set new PC
     Addr HandlerBase;
     // Offset 0x180 - General Exception Vector
-    HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
-    setHandlerPC(HandlerBase,tc);
+    HandlerBase = vect() + tc->readMiscReg(EBase);
+    setHandlerPC(HandlerBase, tc);
 }
 
 void
@@ -308,12 +304,12 @@ AddressErrorFault::invoke(ThreadContext *tc)
 {
     DPRINTF(MipsPRA, "%s encountered.\n", name());
     setExceptionState(tc, 0x4);
-    tc->setMiscRegNoEffect(MipsISA::BadVAddr, BadVAddr);
+    tc->setMiscRegNoEffect(BadVAddr, badVAddr);
 
     // Set new PC
     Addr HandlerBase;
     // Offset 0x180 - General Exception Vector
-    HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
+    HandlerBase = vect() + tc->readMiscReg(EBase);
     setHandlerPC(HandlerBase, tc);
 }
 
@@ -322,50 +318,51 @@ ItbInvalidFault::invoke(ThreadContext *tc)
 {
     DPRINTF(MipsPRA, "%s encountered.\n", name());
     setExceptionState(tc, 0x2);
-    tc->setMiscRegNoEffect(MipsISA::BadVAddr, BadVAddr);
-    MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
-    replaceBits(eh, EntryHi_ASID_HI, EntryHi_ASID_LO, EntryHi_Asid);
-    replaceBits(eh, EntryHi_VPN2_HI, EntryHi_VPN2_LO, EntryHi_VPN2);
-    replaceBits(eh, EntryHi_VPN2X_HI, EntryHi_VPN2X_LO, EntryHi_VPN2X);
-    tc->setMiscRegNoEffect(MipsISA::EntryHi, eh);
-    MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
-    replaceBits(ctxt, Context_BadVPN2_HI, Context_BadVPN2_LO, Context_BadVPN2);
-    tc->setMiscRegNoEffect(MipsISA::Context, ctxt);
+    tc->setMiscRegNoEffect(BadVAddr, badVAddr);
+    EntryHiReg entryHi = tc->readMiscReg(EntryHi);
+    entryHi.asid = entryHiAsid;
+    entryHi.vpn2 = entryHiVPN2;
+    entryHi.vpn2x = entryHiVPN2X;
+    tc->setMiscRegNoEffect(EntryHi, entryHi);
+
+    ContextReg context = tc->readMiscReg(Context);
+    context.badVPN2 = contextBadVPN2;
+    tc->setMiscRegNoEffect(Context, context);
 
 
     // Set new PC
     Addr HandlerBase;
     // Offset 0x180 - General Exception Vector
-    HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase);
+    HandlerBase = vect() + tc->readMiscReg(EBase);
     setHandlerPC(HandlerBase,tc);
-    DPRINTF(MipsPRA,"Exception Handler At: %x , EPC set to %x\n",
-            HandlerBase, tc->readMiscReg(MipsISA::EPC));
+    DPRINTF(MipsPRA, "Exception Handler At: %x , EPC set to %x\n",
+            HandlerBase, tc->readMiscReg(EPC));
 }
 
 void
 ItbRefillFault::invoke(ThreadContext *tc)
 {
-    DPRINTF(MipsPRA, "%s encountered (%x).\n", name(), BadVAddr);
+    DPRINTF(MipsPRA, "%s encountered (%x).\n", name(), badVAddr);
     Addr HandlerBase;
-    tc->setMiscRegNoEffect(MipsISA::BadVAddr, BadVAddr);
-    MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
-    replaceBits(eh, EntryHi_ASID_HI, EntryHi_ASID_LO, EntryHi_Asid);
-    replaceBits(eh, EntryHi_VPN2_HI, EntryHi_VPN2_LO, EntryHi_VPN2);
-    replaceBits(eh, EntryHi_VPN2X_HI, EntryHi_VPN2X_LO, EntryHi_VPN2X);
-    tc->setMiscRegNoEffect(MipsISA::EntryHi, eh);
-    MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
-    replaceBits(ctxt, Context_BadVPN2_HI, Context_BadVPN2_LO, Context_BadVPN2);
-    tc->setMiscRegNoEffect(MipsISA::Context, ctxt);
-
-    MiscReg stat = tc->readMiscReg(MipsISA::Status);
+    tc->setMiscRegNoEffect(BadVAddr, badVAddr);
+    EntryHiReg entryHi = tc->readMiscReg(EntryHi);
+    entryHi.asid = entryHiAsid;
+    entryHi.vpn2 = entryHiVPN2;
+    entryHi.vpn2x = entryHiVPN2X;
+    tc->setMiscRegNoEffect(EntryHi, entryHi);
+    ContextReg context = tc->readMiscReg(Context);
+    context.badVPN2 = contextBadVPN2;
+    tc->setMiscRegNoEffect(Context, context);
+
+    StatusReg status = tc->readMiscReg(Status);
     // Since handler depends on EXL bit, must check EXL bit before setting it!!
     // See MIPS ARM Vol 3, Revision 2, Page 38
-    if (bits(stat, Status_EXL) == 1) {
+    if (status.exl == 1) {
         // Offset 0x180 - General Exception Vector
-        HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
+        HandlerBase = vect() + tc->readMiscReg(EBase);
     } else {
         // Offset 0x000
-        HandlerBase = tc->readMiscReg(MipsISA::EBase);
+        HandlerBase = tc->readMiscReg(EBase);
     }
 
     setExceptionState(tc, 0x2);
@@ -378,25 +375,26 @@ DtbRefillFault::invoke(ThreadContext *tc)
     // Set new PC
     DPRINTF(MipsPRA, "%s encountered.\n", name());
     Addr HandlerBase;
-    tc->setMiscRegNoEffect(MipsISA::BadVAddr, BadVAddr);
-    MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
-    replaceBits(eh, EntryHi_ASID_HI, EntryHi_ASID_LO, EntryHi_Asid);
-    replaceBits(eh, EntryHi_VPN2_HI, EntryHi_VPN2_LO, EntryHi_VPN2);
-    replaceBits(eh, EntryHi_VPN2X_HI, EntryHi_VPN2X_LO, EntryHi_VPN2X);
-    tc->setMiscRegNoEffect(MipsISA::EntryHi, eh);
-    MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
-    replaceBits(ctxt, Context_BadVPN2_HI, Context_BadVPN2_LO, Context_BadVPN2);
-    tc->setMiscRegNoEffect(MipsISA::Context, ctxt);
-
-    MiscReg stat = tc->readMiscReg(MipsISA::Status);
+    tc->setMiscRegNoEffect(BadVAddr, badVAddr);
+    EntryHiReg entryHi = tc->readMiscReg(EntryHi);
+    entryHi.asid = entryHiAsid;
+    entryHi.vpn2 = entryHiVPN2;
+    entryHi.vpn2x = entryHiVPN2X;
+    tc->setMiscRegNoEffect(EntryHi, entryHi);
+
+    ContextReg context = tc->readMiscReg(Context);
+    context.badVPN2 = contextBadVPN2;
+    tc->setMiscRegNoEffect(Context, context);
+
+    StatusReg status = tc->readMiscReg(Status);
     // Since handler depends on EXL bit, must check EXL bit before setting it!!
     // See MIPS ARM Vol 3, Revision 2, Page 38
-    if(bits(stat, Status_EXL) == 1) {
+    if (status.exl) {
         // Offset 0x180 - General Exception Vector
-        HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
+        HandlerBase = vect() + tc->readMiscReg(EBase);
     } else {
         // Offset 0x000
-        HandlerBase = tc->readMiscReg(MipsISA::EBase);
+        HandlerBase = tc->readMiscReg(EBase);
     }
 
     setExceptionState(tc, 0x3);
@@ -408,20 +406,21 @@ void
 TLBModifiedFault::invoke(ThreadContext *tc)
 {
     DPRINTF(MipsPRA, "%s encountered.\n", name());
-    tc->setMiscRegNoEffect(MipsISA::BadVAddr, BadVAddr);
-    MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
-    replaceBits(eh, EntryHi_ASID_HI, EntryHi_ASID_LO, EntryHi_Asid);
-    replaceBits(eh, EntryHi_VPN2_HI, EntryHi_VPN2_LO, EntryHi_VPN2);
-    replaceBits(eh, EntryHi_VPN2X_HI, EntryHi_VPN2X_LO, EntryHi_VPN2X);
-    tc->setMiscRegNoEffect(MipsISA::EntryHi, eh);
-    MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
-    replaceBits(ctxt, Context_BadVPN2_HI, Context_BadVPN2_LO, Context_BadVPN2);
-    tc->setMiscRegNoEffect(MipsISA::Context, ctxt);
+    tc->setMiscRegNoEffect(BadVAddr, badVAddr);
+    EntryHiReg entryHi = tc->readMiscReg(EntryHi);
+    entryHi.asid = entryHiAsid;
+    entryHi.vpn2 = entryHiVPN2;
+    entryHi.vpn2x = entryHiVPN2X;
+    tc->setMiscRegNoEffect(EntryHi, entryHi);
+
+    ContextReg context = tc->readMiscReg(Context);
+    context.badVPN2 = contextBadVPN2;
+    tc->setMiscRegNoEffect(Context, context);
 
     // Set new PC
     Addr HandlerBase;
     // Offset 0x180 - General Exception Vector
-    HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
+    HandlerBase = vect() + tc->readMiscReg(EBase);
     setExceptionState(tc, 0x1);
     setHandlerPC(HandlerBase, tc);
 
@@ -436,7 +435,7 @@ SystemCallFault::invoke(ThreadContext *tc)
     // Set new PC
     Addr HandlerBase;
     // Offset 0x180 - General Exception Vector
-    HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
+    HandlerBase = vect() + tc->readMiscReg(EBase);
     setHandlerPC(HandlerBase, tc);
 }
 
@@ -448,13 +447,13 @@ InterruptFault::invoke(ThreadContext *tc)
     setExceptionState(tc, 0x0A);
     Addr HandlerBase;
 
-    uint8_t IV = bits(tc->readMiscRegNoEffect(MipsISA::Cause), Cause_IV);
-    if (IV) {
+    CauseReg cause = tc->readMiscRegNoEffect(Cause);
+    if (cause.iv) {
         // Offset 200 for release 2
-        HandlerBase = 0x20 + vect() + tc->readMiscRegNoEffect(MipsISA::EBase);
+        HandlerBase = 0x20 + vect() + tc->readMiscRegNoEffect(EBase);
     } else {
         //Ofset at 180 for release 1
-        HandlerBase = vect() + tc->readMiscRegNoEffect(MipsISA::EBase);
+        HandlerBase = vect() + tc->readMiscRegNoEffect(EBase);
     }
 
     setHandlerPC(HandlerBase, tc);
@@ -472,12 +471,13 @@ ResetFault::invoke(ThreadContext *tc)
     tc->setPC(vect());
     tc->setNextPC(vect() + sizeof(MachInst));
     tc->setNextNPC(vect() + sizeof(MachInst) + sizeof(MachInst));
-    DPRINTF(MipsPRA, "(%x)  -  ResetFault::invoke : PC set to %x",
-            (unsigned)tc, (unsigned)tc->readPC());
+    DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", tc->readPC());
 #endif
 
     // Set Coprocessor 1 (Floating Point) To Usable
-    tc->setMiscReg(MipsISA::Status, MipsISA::Status | 0x20000000);
+    StatusReg status = tc->readMiscRegNoEffect(Status);
+    status.cu.cu1 = 1;
+    tc->setMiscReg(Status, status);
 }
 
 void
@@ -488,7 +488,7 @@ ReservedInstructionFault::invoke(ThreadContext *tc)
     setExceptionState(tc, 0x0A);
     Addr HandlerBase;
     // Offset 0x180 - General Exception Vector
-    HandlerBase = vect() + tc->readMiscRegNoEffect(MipsISA::EBase);
+    HandlerBase = vect() + tc->readMiscRegNoEffect(EBase);
     setHandlerPC(HandlerBase, tc);
 #else
     panic("%s encountered.\n", name());
@@ -517,13 +517,13 @@ CoprocessorUnusableFault::invoke(ThreadContext *tc)
     setExceptionState(tc, 0xb);
     // The ID of the coprocessor causing the exception is stored in
     // CoprocessorUnusableFault::coProcID
-    MiscReg cause = tc->readMiscReg(MipsISA::Cause);
-    replaceBits(cause, Cause_CE_HI, Cause_CE_LO, coProcID);
-    tc->setMiscRegNoEffect(MipsISA::Cause, cause);
+    CauseReg cause = tc->readMiscReg(Cause);
+    cause.ce = coProcID;
+    tc->setMiscRegNoEffect(Cause, cause);
 
     Addr HandlerBase;
     // Offset 0x180 - General Exception Vector
-    HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
+    HandlerBase = vect() + tc->readMiscReg(EBase);
     setHandlerPC(HandlerBase, tc);
 
 #else
diff --git a/src/arch/mips/faults.hh b/src/arch/mips/faults.hh
index f2b304e95..7a001d390 100644
--- a/src/arch/mips/faults.hh
+++ b/src/arch/mips/faults.hh
@@ -47,11 +47,11 @@ class MipsFault : public FaultBase
     virtual bool skipFaultingInstruction() {return false;}
     virtual bool setRestartAddress() {return true;}
   public:
-    Addr BadVAddr;
-    Addr EntryHi_Asid;
-    Addr EntryHi_VPN2;
-    Addr EntryHi_VPN2X;
-    Addr Context_BadVPN2;
+    Addr badVAddr;
+    Addr entryHiAsid;
+    Addr entryHiVPN2;
+    Addr entryHiVPN2X;
+    Addr contextBadVPN2;
 #if FULL_SYSTEM
     void invoke(ThreadContext * tc) {};
     void setExceptionState(ThreadContext *, uint8_t);
diff --git a/src/arch/mips/interrupts.cc b/src/arch/mips/interrupts.cc
index 207bb15da..4b1f37856 100755
--- a/src/arch/mips/interrupts.cc
+++ b/src/arch/mips/interrupts.cc
@@ -31,25 +31,26 @@
  *          Korey Sewell
  */
 
-#include "arch/mips/pra_constants.hh"
+#include "arch/mips/interrupts.hh"
 #include "arch/mips/isa_traits.hh"
+#include "arch/mips/pra_constants.hh"
+#include "base/trace.hh"
 #include "cpu/thread_context.hh"
-#include "arch/mips/interrupts.hh"
 
 namespace MipsISA
 {
 
 static inline uint8_t
 getCauseIP(ThreadContext *tc) {
-    MiscReg cause = tc->readMiscRegNoEffect(MipsISA::Cause);
-    return bits(cause, Cause_IP7, Cause_IP0);
+    CauseReg cause = tc->readMiscRegNoEffect(Cause);
+    return cause.ip;
 }
 
 static inline void
-setCauseIP_(ThreadContext *tc, uint8_t val) {
-    MiscReg cause = tc->readMiscRegNoEffect(MipsISA::Cause);
-    replaceBits(cause, Cause_IP7, Cause_IP0, val);
-    tc->setMiscRegNoEffect(MipsISA::Cause, cause);
+setCauseIP(ThreadContext *tc, uint8_t val) {
+    CauseReg cause = tc->readMiscRegNoEffect(Cause);
+    cause.ip = val;
+    tc->setMiscRegNoEffect(Cause, cause);
 }
 
 void
@@ -110,21 +111,17 @@ Interrupts::getInterrupt(ThreadContext * tc)
     DPRINTF(Interrupt, "Interrupts getInterrupt\n");
 
     //Check if there are any outstanding interrupts
-    MiscReg status = tc->readMiscRegNoEffect(MipsISA::Status);
+    StatusReg status = tc->readMiscRegNoEffect(Status);
     // Interrupts must be enabled, error level must be 0 or interrupts
     // inhibited, and exception level must be 0 or interrupts inhibited
-    if (bits(status, Status_IE_LO) == 1 &&
-        bits(status, Status_ERL_HI, Status_ERL_LO) == 0 &&
-        bits(status, Status_EXL_HI, Status_EXL_LO) == 0) {
+    if ((status.ie == 1) && (status.erl == 0) && (status.exl == 0)) {
         // Software interrupts & hardware interrupts are handled in software.
         // So if any interrupt that isn't masked is detected, jump to interrupt
         // handler
-        uint8_t InterruptMask = bits(status, Status_IM7, Status_IM0);
-        uint8_t InterruptPending = getCauseIP(tc);
-        // InterruptMask and InterruptPending are already correctly aligned
-        if (InterruptMask && InterruptPending){
+        CauseReg cause = tc->readMiscRegNoEffect(Cause);
+        if (status.im && cause.ip) {
             DPRINTF(Interrupt, "Interrupt! IM[7:0]=%d IP[7:0]=%d \n",
-                    InterruptMask, InterruptPending);
+                    (unsigned)status.im, (unsigned)cause.ip);
             return new InterruptFault;
         }
     }
@@ -135,8 +132,8 @@ Interrupts::getInterrupt(ThreadContext * tc)
 bool
 Interrupts::onCpuTimerInterrupt(ThreadContext * tc) const
 {
-    MiscReg compare = tc->readMiscRegNoEffect(MipsISA::Compare);
-    MiscReg count = tc->readMiscRegNoEffect(MipsISA::Count);
+    MiscReg compare = tc->readMiscRegNoEffect(Compare);
+    MiscReg count = tc->readMiscRegNoEffect(Count);
     if (compare == count && count != 0)
         return true;
     return false;
@@ -156,13 +153,10 @@ Interrupts::interruptsPending(ThreadContext *tc) const
     if (onCpuTimerInterrupt(tc)) {
         DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc) == true\n");
         //determine timer interrupt IP #
-        MiscReg intctl = tc->readMiscRegNoEffect(MipsISA::IntCtl);
-        uint8_t IPTI = bits(intctl, IntCtl_IPTI_HI, IntCtl_IPTI_LO);
-        //set intstatus to correspond
-        //post(IPTI, tc);
-        uint8_t intstatus = getCauseIP(tc);
-        intstatus |= 1 << IPTI;
-        setCauseIP(tc, intstatus);
+        IntCtlReg intCtl = tc->readMiscRegNoEffect(IntCtl);
+        uint8_t intStatus = getCauseIP(tc);
+        intStatus |= 1 << intCtl.ipti;
+        setCauseIP(tc, intStatus);
     }
 
     return (getCauseIP(tc) != 0);
@@ -170,3 +164,9 @@ Interrupts::interruptsPending(ThreadContext *tc) const
 }
 
 }
+
+MipsISA::Interrupts *
+MipsInterruptsParams::create()
+{
+    return new MipsISA::Interrupts(this);
+}
diff --git a/src/arch/mips/interrupts.hh b/src/arch/mips/interrupts.hh
index 13d4f8512..c852bc9d0 100755
--- a/src/arch/mips/interrupts.hh
+++ b/src/arch/mips/interrupts.hh
@@ -31,20 +31,41 @@
 #ifndef __ARCH_MIPS_INTERRUPT_HH__
 #define __ARCH_MIPS_INTERRUPT_HH__
 
+#include <string>
+
 #include "arch/mips/faults.hh"
 #include "base/compiler.hh"
+#include "base/misc.hh"
+#include "params/MipsInterrupts.hh"
+#include "sim/serialize.hh"
+#include "sim/sim_object.hh"
+
+class BaseCPU;
+class Checkpoint;
 
 namespace MipsISA
 {
 
-class Interrupts
+class Interrupts : public SimObject
 {
   public:
-    Interrupts()
+    typedef MipsInterruptsParams Params;
+
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
+
+    Interrupts(Params * p) : SimObject(p)
     {
         newInfoSet = false;
     }
 
+    void
+    setCPU(BaseCPU *_cpu)
+    {}
+
     //  post(int int_num, int index) is responsible
     //  for posting an interrupt. It sets a bit
     //  in intstatus corresponding to Cause IP*. The
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 7a6d5db05..60bc15513 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -771,7 +771,7 @@ decode OPCODE_HI default Unknown::unknown() {
                     NewEntry.OffsetMask = ((1<<NewEntry.AddrShiftAmount)-1);
 
                     MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr();
-                    Config3Reg config3 = Config3
+                    Config3Reg config3 = Config3;
                     PageGrainReg pageGrain = PageGrain;
                     int SP = 0;
                     if (bits(config3, config3.sp) == 1 &&
@@ -836,7 +836,7 @@ decode OPCODE_HI default Unknown::unknown() {
                     NewEntry.OffsetMask = ((1 << NewEntry.AddrShiftAmount) - 1);
 
                     MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr();
-                    Config3Reg config3 = Config3
+                    Config3Reg config3 = Config3;
                     PageGrainReg pageGrain = PageGrain;
                     int SP = 0;
                     if (bits(config3, config3.sp) == 1 &&
diff --git a/src/arch/mips/pra_constants.hh b/src/arch/mips/pra_constants.hh
index 129f4185f..971501493 100755
--- a/src/arch/mips/pra_constants.hh
+++ b/src/arch/mips/pra_constants.hh
@@ -120,14 +120,16 @@ BitUnion32(StatusReg)
     // Bit 18 is zero
     Bitfield<17, 16> impl;
     Bitfield<15, 10> ipl;
-    Bitfield<15>     im7;
-    Bitfield<14>     im6;
-    Bitfield<13>     im5;
-    Bitfield<12>     im4;
-    Bitfield<11>     im3;
-    Bitfield<10>     im2;
-    Bitfield<9>      im1;
-    Bitfield<8>      im0;
+    SubBitUnion(im, 15, 8)
+        Bitfield<15> im7;
+        Bitfield<14> im6;
+        Bitfield<13> im5;
+        Bitfield<12> im4;
+        Bitfield<11> im3;
+        Bitfield<10> im2;
+        Bitfield<9>  im1;
+        Bitfield<8>  im0;
+    EndSubBitUnion(im)
     Bitfield<7>      kx;
     Bitfield<6>      sx;
     Bitfield<5>      ux;
@@ -182,14 +184,16 @@ BitUnion32(CauseReg)
     Bitfield<22>     wp;
     // Bits 21-16 are zeros
     Bitfield<15, 10> ripl;
-    Bitfield<15>     ip7;
-    Bitfield<14>     ip6;
-    Bitfield<13>     ip5;
-    Bitfield<12>     ip4;
-    Bitfield<11>     ip3;
-    Bitfield<10>     ip2;
-    Bitfield<9>      ip1;
-    Bitfield<8>      ip0;
+    SubBitUnion(ip, 15, 8)
+        Bitfield<15> ip7;
+        Bitfield<14> ip6;
+        Bitfield<13> ip5;
+        Bitfield<12> ip4;
+        Bitfield<11> ip3;
+        Bitfield<10> ip2;
+        Bitfield<9>  ip1;
+        Bitfield<8>  ip0;
+    EndSubBitUnion(ip);
     // Bit 7 is zero
     Bitfield<6,  2>  excCode;
     // Bits 1-0 are zeros
diff --git a/src/arch/mips/system.cc b/src/arch/mips/system.cc
index ac900b6db..57310fa77 100755
--- a/src/arch/mips/system.cc
+++ b/src/arch/mips/system.cc
@@ -51,7 +51,7 @@ MipsSystem::MipsSystem(Params *p) : System(p)
 #if FULL_SYSTEM
     if (p->bare_iron == true) {
         hexFile = new HexFile(params()->hex_file_name);
-        if (!hexFile->loadSections(&functionalPort, MipsISA::LoadAddrMask))
+        if (!hexFile->loadSections(&functionalPort))
             panic("Could not load hex file\n");
     }
 
@@ -93,7 +93,6 @@ MipsSystem::MipsSystem(Params *p) : System(p)
      */
     if (consoleSymtab->findAddress("env_booted_osflags", addr)) {
         warn("writing addr starting from %#x", addr);
-        cout << "-" << endl;
         virtPort.writeBlob(addr, (uint8_t*)params()->boot_osflags.c_str(),
                 strlen(params()->boot_osflags.c_str()));
     }
diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index 3a8d400ae..37c1ecee3 100644
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -315,7 +315,7 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
                 req->isMisaligned()) {
             AddressErrorFault *Flt = new AddressErrorFault();
             /* BadVAddr must be set */
-            Flt->BadVAddr = req->getVaddr();
+            Flt->badVAddr = req->getVaddr();
             return Flt;
         }
     } else if(IsKSeg1(req->getVaddr())) {
@@ -338,7 +338,7 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
           // Unaligned address!
           AddressErrorFault *Flt = new AddressErrorFault();
           /* BadVAddr must be set */
-          Flt->BadVAddr = req->getVaddr();
+          Flt->badVAddr = req->getVaddr();
           return Flt;
       }
       PTE *pte = lookup(VPN,Asid);
@@ -361,15 +361,15 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
               //Invalid entry
               ItbInvalidFault *Flt = new ItbInvalidFault();
               /* EntryHi VPN, ASID fields must be set */
-              Flt->EntryHi_Asid = Asid;
-              Flt->EntryHi_VPN2 = (VPN >> 2);
-              Flt->EntryHi_VPN2X = (VPN & 0x3);
+              Flt->entryHiAsid = Asid;
+              Flt->entryHiVPN2 = (VPN >> 2);
+              Flt->entryHiVPN2X = (VPN & 0x3);
 
               /* BadVAddr must be set */
-              Flt->BadVAddr = req->getVaddr();
+              Flt->badVAddr = req->getVaddr();
 
               /* Context must be set */
-              Flt->Context_BadVPN2 = (VPN >> 2);
+              Flt->contextBadVPN2 = (VPN >> 2);
               return Flt;
           } else {
               // Ok, this is really a match, set paddr
@@ -388,15 +388,15 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
             // Didn't find any match, return a TLB Refill Exception
             ItbRefillFault *Flt=new ItbRefillFault();
             /* EntryHi VPN, ASID fields must be set */
-            Flt->EntryHi_Asid = Asid;
-            Flt->EntryHi_VPN2 = (VPN >> 2);
-            Flt->EntryHi_VPN2X = (VPN & 0x3);
+            Flt->entryHiAsid = Asid;
+            Flt->entryHiVPN2 = (VPN >> 2);
+            Flt->entryHiVPN2X = (VPN & 0x3);
 
             /* BadVAddr must be set */
-            Flt->BadVAddr = req->getVaddr();
+            Flt->badVAddr = req->getVaddr();
 
             /* Context must be set */
-            Flt->Context_BadVPN2 = (VPN >> 2);
+            Flt->contextBadVPN2 = (VPN >> 2);
             return Flt;
         }
     }
@@ -435,7 +435,7 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
                 req->isMisaligned()) {
             StoreAddressErrorFault *Flt = new StoreAddressErrorFault();
             /* BadVAddr must be set */
-            Flt->BadVAddr = req->getVaddr();
+            Flt->badVAddr = req->getVaddr();
 
             return Flt;
         }
@@ -458,7 +458,7 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
             // Unaligned address!
             StoreAddressErrorFault *Flt = new StoreAddressErrorFault();
             /* BadVAddr must be set */
-            Flt->BadVAddr = req->getVaddr();
+            Flt->badVAddr = req->getVaddr();
             return Flt;
         }
         if (pte != NULL) {
@@ -483,15 +483,15 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
                 //Invalid entry
                 DtbInvalidFault *Flt = new DtbInvalidFault();
                 /* EntryHi VPN, ASID fields must be set */
-                Flt->EntryHi_Asid = Asid;
-                Flt->EntryHi_VPN2 = (VPN>>2);
-                Flt->EntryHi_VPN2X = (VPN & 0x3);
+                Flt->entryHiAsid = Asid;
+                Flt->entryHiVPN2 = (VPN>>2);
+                Flt->entryHiVPN2X = (VPN & 0x3);
 
                 /* BadVAddr must be set */
-                Flt->BadVAddr = req->getVaddr();
+                Flt->badVAddr = req->getVaddr();
 
                 /* Context must be set */
-                Flt->Context_BadVPN2 = (VPN >> 2);
+                Flt->contextBadVPN2 = (VPN >> 2);
 
                 return Flt;
             } else {
@@ -499,15 +499,15 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
                 if (!Dirty) {
                     TLBModifiedFault *Flt = new TLBModifiedFault();
                     /* EntryHi VPN, ASID fields must be set */
-                    Flt->EntryHi_Asid = Asid;
-                    Flt->EntryHi_VPN2 = (VPN >> 2);
-                    Flt->EntryHi_VPN2X = (VPN & 0x3);
+                    Flt->entryHiAsid = Asid;
+                    Flt->entryHiVPN2 = (VPN >> 2);
+                    Flt->entryHiVPN2X = (VPN & 0x3);
 
                     /* BadVAddr must be set */
-                    Flt->BadVAddr = req->getVaddr();
+                    Flt->badVAddr = req->getVaddr();
 
                     /* Context must be set */
-                    Flt->Context_BadVPN2 = (VPN >> 2);
+                    Flt->contextBadVPN2 = (VPN >> 2);
                     return Flt;
                 }
                 Addr PAddr;
@@ -525,15 +525,15 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
             // Didn't find any match, return a TLB Refill Exception
             DtbRefillFault *Flt = new DtbRefillFault();
             /* EntryHi VPN, ASID fields must be set */
-            Flt->EntryHi_Asid = Asid;
-            Flt->EntryHi_VPN2 = (VPN >> 2);
-            Flt->EntryHi_VPN2X = (VPN & 0x3);
+            Flt->entryHiAsid = Asid;
+            Flt->entryHiVPN2 = (VPN >> 2);
+            Flt->entryHiVPN2X = (VPN & 0x3);
 
             /* BadVAddr must be set */
-            Flt->BadVAddr = req->getVaddr();
+            Flt->badVAddr = req->getVaddr();
 
             /* Context must be set */
-            Flt->Context_BadVPN2 = (VPN >> 2);
+            Flt->contextBadVPN2 = (VPN >> 2);
             return Flt;
         }
     }
diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc
index 4723d6301..ac90ce45e 100644
--- a/src/arch/mips/utility.cc
+++ b/src/arch/mips/utility.cc
@@ -38,6 +38,7 @@
 #include "base/misc.hh"
 
 #if FULL_SYSTEM
+#include "arch/mips/registers.hh"
 #include "arch/mips/vtophys.hh"
 #include "mem/vport.hh"
 #endif
@@ -52,16 +53,16 @@ uint64_t
 getArgument(ThreadContext *tc, int number, bool fp)
 {
 #if FULL_SYSTEM
-    if (number < NumArgumentRegs) {
+    if (number < 4) {
         if (fp)
-            return tc->readFloatRegBits(ArgumentReg[number]);
+            return tc->readFloatRegBits(FirstArgumentReg + number);
         else
-            return tc->readIntReg(ArgumentReg[number]);
+            return tc->readIntReg(FirstArgumentReg + number);
     } else {
         Addr sp = tc->readIntReg(StackPointerReg);
         VirtualPort *vp = tc->getVirtPort();
         uint64_t arg = vp->read<uint64_t>(sp +
-                           (number-NumArgumentRegs) * sizeof(uint64_t));
+                (number - 4) * sizeof(uint64_t));
         return arg;
     }
 #else