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authorGabe Black <gblack@eecs.umich.edu>2007-07-26 22:03:19 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-07-26 22:03:19 -0700
commit7d826f632cdffbf604661be26f5aab9fbd2466c3 (patch)
tree17ea87f9cfc9d98a11bb9e07c343c0f67ddcdda7 /src/arch
parent26b1c455e0aed69eda0cc165b5084edb1b557c38 (diff)
downloadgem5-7d826f632cdffbf604661be26f5aab9fbd2466c3.tar.xz
Implement NOT
--HG-- extra : convert_revision : 09cbed6332224d06644d401f21178eb7914993df
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/x86/isa/insts/logical.py31
1 files changed, 23 insertions, 8 deletions
diff --git a/src/arch/x86/isa/insts/logical.py b/src/arch/x86/isa/insts/logical.py
index 04737edd1..bbc15f8fa 100644
--- a/src/arch/x86/isa/insts/logical.py
+++ b/src/arch/x86/isa/insts/logical.py
@@ -221,12 +221,27 @@ def macroop AND_P_R
and t1, t1, reg
st t1, ds, [scale, index, base], disp
};
+
+def macroop NOT_R
+{
+ limm t1, -1
+ xor reg, reg, t1
+};
+
+def macroop NOT_M
+{
+ limm t1, -1
+ ld t2, ds, [scale, index, base], disp
+ xor t2, t2, t1
+ st t2, ds, [scale, index, base], disp
+};
+
+def macroop NOT_P
+{
+ limm t1, -1
+ rdip t7
+ ld t2, ds, [0, t0, t7], disp
+ xor t2, t2, t1
+ st t2, ds, [0, t0, t7], disp
+};
'''
-#let {{
-#microcodeString = '''
-# def macroop NOT
-# {
-# Xor reg reg "0xFFFFFFFFFFFFFFFFULL"
-# };
-#'''
-#}};