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authorLisa Hsu <hsul@eecs.umich.edu>2006-12-13 17:51:28 -0500
committerLisa Hsu <hsul@eecs.umich.edu>2006-12-13 17:51:28 -0500
commit98bb1c62b31e988f81d9fc03cf14aca25fd008db (patch)
tree2d26f2c96bf4b4698f0386805c3bfa31c561a038 /src/arch
parentbc05f5982e8ac89f3e11e3aa3853e651a644778a (diff)
downloadgem5-98bb1c62b31e988f81d9fc03cf14aca25fd008db.tar.xz
fix MiscRegFile::readRegWithEffect, which neglected the MISCREGS.
--HG-- extra : convert_revision : 4fdffe01b8e63e24b97a2e4194c747e6cf5e25ba
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/alpha/miscregfile.cc20
1 files changed, 17 insertions, 3 deletions
diff --git a/src/arch/alpha/miscregfile.cc b/src/arch/alpha/miscregfile.cc
index 962d4609f..67f6c98e4 100644
--- a/src/arch/alpha/miscregfile.cc
+++ b/src/arch/alpha/miscregfile.cc
@@ -89,12 +89,26 @@ namespace AlphaISA
MiscReg
MiscRegFile::readRegWithEffect(int misc_reg, ThreadContext *tc)
{
+ switch(misc_reg) {
+ case MISCREG_FPCR:
+ return fpcr;
+ case MISCREG_UNIQ:
+ return uniq;
+ case MISCREG_LOCKFLAG:
+ return lock_flag;
+ case MISCREG_LOCKADDR:
+ return lock_addr;
+ case MISCREG_INTR:
+ return intr_flag;
#if FULL_SYSTEM
- return readIpr(misc_reg, tc);
+ default:
+ return readIpr(misc_reg, tc);
#else
- panic("No faulting misc regs in SE mode!");
- return 0;
+ default:
+ panic("No faulting misc regs in SE mode!");
+ return 0;
#endif
+ }
}
void