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author | Gabe Black <gblack@eecs.umich.edu> | 2006-11-10 05:49:16 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2006-11-10 05:49:16 -0500 |
commit | 9ef51f2dbaba88c10366d708f0ca872bb39064e4 (patch) | |
tree | 31c5289651249ec05162f814d784b90f8737634a /src/arch | |
parent | 9731fb3fd72ed2e8f5bf3423a33d45a5c35f636f (diff) | |
download | gem5-9ef51f2dbaba88c10366d708f0ca872bb39064e4.tar.xz |
Actually finished moving the register file stuff around.
--HG--
extra : convert_revision : 786735ecea8ff480db6b3754ac5daa562938d988
Diffstat (limited to 'src/arch')
-rw-r--r-- | src/arch/alpha/floatregfile.hh | 5 | ||||
-rw-r--r-- | src/arch/alpha/intregfile.hh | 5 | ||||
-rw-r--r-- | src/arch/alpha/miscregfile.hh | 5 | ||||
-rw-r--r-- | src/arch/alpha/regfile.hh | 33 |
4 files changed, 16 insertions, 32 deletions
diff --git a/src/arch/alpha/floatregfile.hh b/src/arch/alpha/floatregfile.hh index 6b394da03..d289f5785 100644 --- a/src/arch/alpha/floatregfile.hh +++ b/src/arch/alpha/floatregfile.hh @@ -42,6 +42,11 @@ class Checkpoint; namespace AlphaISA { + static inline std::string getFloatRegName(RegIndex) + { + return ""; + } + class FloatRegFile { public: diff --git a/src/arch/alpha/intregfile.hh b/src/arch/alpha/intregfile.hh index 78f666345..0d65f69e0 100644 --- a/src/arch/alpha/intregfile.hh +++ b/src/arch/alpha/intregfile.hh @@ -41,6 +41,11 @@ class Checkpoint; namespace AlphaISA { + static inline std::string getIntRegName(RegIndex) + { + return ""; + } + // redirected register map, really only used for the full system case. extern const int reg_redir[NumIntRegs]; diff --git a/src/arch/alpha/miscregfile.hh b/src/arch/alpha/miscregfile.hh index 85cb054bb..31b3e59b3 100644 --- a/src/arch/alpha/miscregfile.hh +++ b/src/arch/alpha/miscregfile.hh @@ -54,6 +54,11 @@ namespace AlphaISA MISCREG_INTR }; + static inline std::string getMiscRegName(RegIndex) + { + return ""; + } + class MiscRegFile { protected: uint64_t fpcr; // floating point condition codes diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh index 091f0e2e6..ff5830822 100644 --- a/src/arch/alpha/regfile.hh +++ b/src/arch/alpha/regfile.hh @@ -32,6 +32,7 @@ #define __ARCH_ALPHA_REGFILE_HH__ #include "arch/alpha/isa_traits.hh" +#include "arch/alpha/floatregfile.hh" #include "arch/alpha/intregfile.hh" #include "arch/alpha/miscregfile.hh" #include "arch/alpha/types.hh" @@ -47,38 +48,6 @@ class ThreadContext; namespace AlphaISA { - static inline std::string getIntRegName(RegIndex) - { - return ""; - } - - static inline std::string getFloatRegName(RegIndex) - { - return ""; - } - - static inline std::string getMiscRegName(RegIndex) - { - return ""; - } - - class FloatRegFile - { - public: - - union { - uint64_t q[NumFloatRegs]; // integer qword view - double d[NumFloatRegs]; // double-precision floating point view - }; - - void serialize(std::ostream &os); - - void unserialize(Checkpoint *cp, const std::string §ion); - - void clear() - { bzero(d, sizeof(d)); } - }; - class RegFile { protected: |